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We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (rhoc), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective...
A novel low voltage base modulated SCR has been developed using a triple well CMOS process. External control circuits modulate the base pwell resistance, reduce the trigger currents from milliamps to microamps, and decouple holding and trigger voltages of the SCR during both ESD events and normal circuit operations.
Control of reliability is a major economic and technical challenge for power electronics. Today, models can be used to predict failure, but to be accurate this models should be updated continuously by the real mechanical state of the device. A possible solution is to make use of the silicon piezoresistive properties of MOS gated power devices (LDMOS, VDMOS, ...) and to take advantage, without increasing...
We use infrared microscopy to image the temperature profile of graphene field-effect transistors operating at constant source to drain current bias. We find a peak in the temperature profile, i.e. a ??hot spot?? appears near the drain (anode) electrode of the graphene sheet at high current while operating in the hole-doped regime. We shift the hot spot position on the graphene sheet by tuning the...
The ballistic efficiency and self-heating effects in gate-all-around silicon nanowire transistors (SNWTs) are experimentally investigated in this paper. A modified experimental extraction method for SNWTs is proposed, which takes into account the impact of source contact resistance. The highest ballistic efficiency is observed in sub-40 nm SNWTs at room temperature, demonstrating their intrinsic potential...
We demonstrated for the first time the device performance of (110) nMOSFETs featuring a Si migration process, resulting in better mobility and modified shape of the narrow active region, and ultra-shallow Al implantation after nickel silicide (NiSi) formation, resulting in reduced parasitic resistance. We found that these processes made the performance of (110) nMOSFETs competitive with that of (001)...
After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
Low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with metal-replaced source and drain regions have been fabricated and characterized. Several technological schemes for replacing poly-Si with aluminum have been investigated and the relative merits of each are compared.
In this work a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices, where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.
Metal-oxide-silicon(MOS) capacitors incorporating 2 ~ 3 germanium (Ge) quantum dots (QDs) in the gate oxide were fabricated to exhibit multi-peak negative differential resistance (NDR) for multiple-value memories and logics. The tunneling current through the Ge-QD MOS capacitors is theoretically and experimentally studied. We found that negative differential resistance (NDR) arises from the interdot...
We have successfully fabricated uniaxially strained SOI FinFETs with high electron mobility and low parasitic resistance. The electron mobility on (110) sidewall surfaces was found to surpass the (100) universal mobility by the subband engineering through uniaxial tensile strain along <110>. Thanks to this high electron mobility enhancement and the relatively low parasitic resistance, high I...
There is a growing belief that strained silicon alone may not be able to deliver sufficient performance beyond the 22nm technology generation of the International Technology Roadmap for Semiconductors (ITRS), and that high mobility channel materials may be required. This view has led to the establishment of various collaborations to explore the potential of high mobility III-V semiconductors, particularly...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
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