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We address the problem of routing for multi-radio multi-channel wireless mesh networks, and propose a novel routing metric, named DARM. Compared with the prior routing metrics focus on the network throughput, DARM aims to minimize the end-to-end delay, which is a significant requirement for multimedia applications. Our routing metric captures the effects of variation in link loss-ratio, the length...
This paper proposes a novel analytical model for predicting average message latency under different traffic load in a network-on-chip where wormhole switching and fully adaptive routing protocols are used. The model has simple close-form calculations and yields extremely accurate results in the network stable regions. The validity of this model is shown by comparing analytical results with simulation...
With the increasing number of processor cores in chip multi-processors (CMPs), 2D Mesh has been gaining wide acceptance for inter-core on-chip communication. Program performance is more sensitive to the router latency than to the link bandwidth. This paper presents a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead...
New architectures have recently been proposed and deployed to support end-to-end advance reservation of network resources. These architectures rely on the use a centralized scheduler, which may be unpractical in large or administratively heterogeneous networks. In this work, we explore and demonstrate the feasibility of implementing distributed solutions for advance reservation. We introduce a new...
The protocol stack plays a critical role in determining the performance of Networked Control System (NCS), which governs the communication activities and directly affects the communication Quality of Service (QoS). Full or partial reconfiguration of protocol stack offers both optimized communication service and system performance. This paper proposes a formal approach for the design and implementation...
Each node equipped with multiple interfaces in multi-channel wireless mesh networks can increase the network throughput when applied to appropriate channel assignment and routing protocols. In this paper, we analyze the channel assignment and channel switching problems in WMN where the number of interfaces is smaller than the number of channels. Ripple effect caused by channel switching is presented...
The uneven deployment of wireless sensor networks and the breakdown of sensor nodes often lead to the presence of holes in their topology. Two important factors considered in designing a geographic routing algorithm are overhead and success rate of packet routing. Therefore, in this paper, we present a novel strategy to aid a routing algorithm improve its performance by increasing success rate of...
The Wave Dynamic Differential Logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design....
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process...
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multi-core processors. However the virtual-channel (VC) buffers in...
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency...
The Wave Dynamic Differential Logic (WDDL) is a promising countermeasure to protect cryptographic devices from Differential Power Attacks (DPA). But the key challenge is to maintain symmetry between dual networks, so as to obtain equal propagation delays and power consumption on differential signals. In this paper, we deal with the problem of timing unbalance. We study the impact of different placement...
Implementing multiple channels among the multi-radio nodes of wireless mesh networks (WMNs) improve the capacity of the network. In this paper, we propose channel aware routing metric (CARM) as a new routing metric that facilitates the use of available channels in 802.11 WMNs. It chooses a route that has better link quality, reduced switching delay and better channel diversity. Unlike all the other...
In this article and as a generalization to our work in Fayza et al. (2003), we present a case study of ATM buffers with batch arrivals, geometric service time and priority scheduling. Packets belongs to two classes, class-1 packets represents real time traffics which is delay sensitive but loss insensitive, and class-2 packets represents non real time traffics which is delay insensitive but loss sensitive...
The Internet growth coupled with the variety of its services is creating an increasing need for multicast traffic support by backbone routers and packet switches. Recently, buffered crossbar (CICQ) switches have shown high potential in efficiently handling multicast traffic. However, they were unable to deliver optimal performance despite their expensive and complex crossbar fabric. This paper proposes...
In cognitive radio networks, the new open spectrum operation necessitates novel routing protocols to exploit the available spectrum opportunistically. But due to the non-interfering requirement, a spectrum band used by secondary users may be unexpectedly preempted by primary users at any time, which challenges reliable communications. In this paper, we propose a novel spectrum aware on-demand routing...
Reconfigurability refers to systems incorporating some form of hardware programmability, that customizes how the hardware is used using a number of physical control points. These control points can be changed periodically in order to execute different applications using the same hardware. This paper presents the design and implementation of reconfigurable switch architecture for next generation networks...
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