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This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed...
3D technology is an attractive solution for reducing wirelength in a field programmable gate array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we propose a tilable switch module architecture based on the 3D disjoint switch module for 3D FPGAs. Experimental results over 20 MCNC benchmarks show 62% reduction in the number of TSVs on average and small improvements...
Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently; synthesis converts the design description into a technology-dependent netlist and then physical design takes the fixed netlist, produces layout, and schedules the netlist on the layout. This style of design suffers from limiting the optimization process...
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling-aware register placement algorithm that enables clock...
Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient Toffoli-based synthesis algorithm for reversible circuits...
It has been shown that several process parameters encounter variation in the very deep submicron era. Due to the increased power and performance variability, a multi-objective variability-aware yield optimization method is crucial. However, most of current yield optimization methods use greedy single objective optimization approach. In this paper, a comprehensive and multi-objective yield optimization...
Interconnect mis-prediction is a dominant problem in nanoscale design that may weaken the quality of physical design algorithms or may even increase the design divergence possibility. In this paper, a new interconnect planning technique is presented based highway-on-chip approach. In this methodology, some highways are planned on chip and the location and amount of resource in highways are gradually...
Existing synthesis-related cost functions are explored and five fundamental properties of an efficient quantum circuit implementation are introduced. In addition, a thorough set of metrics for quantum circuit synthesis are proposed and applied on some well-known synthesis algorithms. Our analysis reveals the requirement of proposing new synthesis algorithms to produce realizable circuits. A new heuristic...
The design of clock distribution networks in synchronous digital systems presents great challenges. In other words, controlling the clock signal delay in the presence of process parameter variations is a major problem in the design of high-speed synchronous circuits. In this paper, an efficient algorithm is presented to improve the tolerance of a clock distribution network against process variation...
In this paper, a simple and fast algorithm for the synthesis of reversible circuits is presented. This algorithm considers the synthesis process as a kind of sorting problem, generating a reversible circuit composed of CNOT-based gates. We prove that the proposed algorithm converges for any given specification. The empirical results of realizing examples discussed in the literature are reported. The...
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of...
In this paper, a probabilistic method is introduced to estimate intra-grid wirelength of nets after placement and global routing. In addition, a crosstalk reduction scheme is proposed based on our estimations and a resultant crosstalk map. Our wirelength estimations incorporated with the previous crosstalk estimation schemes, efficiently detect failing noisy nets before detailed routing and full extraction...
Retiming is a well known method for improving the performance of sequential circuits. However, maximum cycle ratio (MCR) is one of the most serious restrictions to be considered by retiming-based techniques. As MCR is proportional to the critical cycle delay, finding shortcut paths to reduce the length of critical cycle can improve the circuit performance. In this paper, Shannon decomposition is used...
It has been shown that several process parameters encounter variation in the DSM era. Consequently, several techniques, such as statistical gate sizing and clock skew scheduling, have been proposed to enhance yield loss. In this work, we propose an integrated statistical framework for gate sizing and skew scheduling in order to minimize yield loss and area cost. While traditional separate methods...
A memory-efficient representation scheme, shared-PPRM (SPPRM), for Boolean reversible functions is introduced and analyzed. Compared with conventional PPRM expansion, SPPRM reduces memory usages by using one memory location for many repetitive PPRM sub-expressions. To evaluate the effects of data structure on SPPRM representation, two linked list-based data structures are also examined. The experimental...
Due to the increasing number of elements on a single chip area and the growing complexity of routing, existing methods to reduce crosstalk at the routing or post-routing stage do not seem efficient anymore. So crosstalk estimation should be considered in earlier design stages such as placement. To estimate crosstalk after placement information about the topology of a net and adjacency of its wire-segments...
In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design space exploration as an alternative to the quantitative approach can be employed to find a right balance between the different design parameters. In this paper, a hybrid approach is introduced to analytically explore the design...
In this paper, a new non-search based synthesis algorithm for reversible circuits is proposed. Compared with the widely used search-based methods, our algorithm is guaranteed to produce a result and can lead to a solution with much fewer steps. To evaluate the proposed method, several circuits taken from the literature are used. The experimental results corroborate the expected findings.
The exponential speed up of quantum algorithms and the fundamental limits of current CMOS process for future design technology have directed attentions toward quantum circuits. In this paper, the matrix specification of a broad category of quantum circuits, i.e. CNOT-based circuits, are investigated. We prove that the matrix elements of CNOT-based circuits can only be zeros or ones. In addition, the...
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