Search results for: K. Goossens

Items from 1 to 20 out of 56 results

article

The effect of maize silage type on the performances and methane emission of dairy cattle

J. L. De Boever, K. Goossens, N. Peiren, J. Swanckaert, more

Journal of Animal Physiology and Animal Nutrition > 101 > 5 > e246 - e256

To examine whether type of maize silage is important for milk production performances, maize silage LG30224 (LG) was compared with Falkone (FA), the latter having a 4.0% points lower rumen NDF digestibility and 19 g/kg dry matter (DM) more starch. To bridge the lower energy content of FA, a third treatment was involved by adding maize meal (MM) in a ratio of 92/8 on DM (FA+MM). Maize and grass silage...

article

Reduction of Mycobacterium avium ssp. paratuberculosis in colostrum: Development and validation of 2 methods, one based on curdling and one based on centrifugation

M. Verhegghe, G. Rasschaert, L. Herman, K. Goossens, more

Journal of Dairy Science > 2017 > 100 > 5 > 3497-3512

The aim of this study was to develop and validate 2 protocols (for use on-farm and at a central location) for the reduction of Mycobacterium avium ssp. paratuberculosis (MAP) in colostrum while preserving beneficial immunoglobulins (IgG). The on-farm protocol was based on curdling of the colostrum, where the IgG remain in the whey and the MAP bacteria are trapped in the curd. First, the colostrum...

article

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays

J.Y. Hur, K. Goossens, L. Mhamdi, M.A. Wahlah

IET Computers & Digital Techniques > 2012 > 6 > 6 > 396 - 405

It is well-known that any logical functionality can be implemented using the reconfigurability in field-programmable gate arrays (FPGAs). However, the reconfigurability is traded with the reduced functional performance, increased cost and increased configuration overheads. Hardwiring the interconnect fabric is gaining notice as an alternative solution to tackle the mentioned problems. In this article,...

article

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

J.Y. Hur, T. Stefanov, S. Wong, K. Goossens

IET Computers & Digital Techniques > 2012 > 6 > 1 > 59 - 68

Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where...

article

The Importance of Adequate Fixation for Immunofluorescent Staining of Bovine Embryos

K Goossens, L Vandaele, E Wydooghe, M Thys, more

Reproduction in Domestic Animals > 46 > 6 > 1098 - 1103

Immunofluorescent staining is often used to investigate the expression of specific proteins in pre‐implantation embryos. The success of this method is determined by the specificity of the antibodies, but also by the protocol used for fixation and permeabilization of the samples. In this study, different fixatives are compared in combination with immunofluorescent staining of caudal‐type homeobox 2...

article

A TDM slot allocation flow based on multipath routing in NoCs

R. Stefan, K. Goossens

Microprocessors and Microsystems > 2011 > 35 > 2 > 130-138

Networks-on-chip have evolved as the natural solution for a scalable interconnect that can be automatically generated to suit the needs of the desired application. In this study we focus on improving the efficiency of on-chip networks using alternative routing strategies. We focus on a multi-path slot allocation method in networks with static resource reservations, in particular TDM NoCs. The simplicity...

article

Interactive Debug of SoCs with Multiple Clocks

B Vermeulen, K Goossens

IEEE Design & Test of Computers > 2011 > 28 > 3 > 44 - 51

Systems with elaborate multiple clock distributions are a necessity, and the authors address the postfabrication debug of such multiclock systems. Solutions, based on the authors' communication-centric debug approach, are presented that achieve a consistent snapshot of the system state and force the erroneous state in the face of nondeterminism.

chapter

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

A B Nejad, M E Martinez, K Goossens

2011 Design, Automation&Test in Europe > 1 - 6

2011 Design, Automation & Test in Europe

FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board...

chapter

Optimal scheduling of switched FlexRay networks

T Schenkelaars, B Vermeulen, K Goossens

2011 Design, Automation&Test in Europe > 1 - 6

2011 Design, Automation & Test in Europe

This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent star coupler, called a switch, to temporarily decouple network branches, thereby increasing the effective network bandwidth. Although scheduling for basic FlexRay networks is not new, prior work in this...

chapter

Architectures and modeling of predictable memory controllers for improved system integration

B Akesson, K Goossens

2011 Design, Automation&Test in Europe > 1 - 6

2011 Design, Automation & Test in Europe

Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with realtime requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified...

chapter

Conservative application-level performance analysis through simulation of MPSoCs

A Nelson, A Hansson, H Corporaal, K Goossens

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia > 51 - 60

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2010)

Applications, often with real-time requirements, are mapped onto Multiprocessor Systems on Chip (MPSoCs). Hard real-time applications require no deadline misses, and a formal modelling approach must be used to analyse the worst-case performance, which is complicated and time consuming. Such models are restricted to specific application behaviours and not generally applicable. Soft real-time applications...

chapter

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

K Goossens, D She, A Milutinovic, A Molnos

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools > 107 - 114

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)

Composability means that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. It is required to be able to design, test, and verify applications independently. In this paper we define composable dynamic voltage and frequency scaling (DVFS) hardware, and composable power management. We ensure that the functional and temporal behaviours...

chapter

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

B Vermeulen, K Goossens

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) > 1 - 8

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT 2010)

Post-silicon debugging of a system on chip (SOC) is complex due to (1) the intrinsic limits on the internal observability, (2) the absence of a single global clock, and (3) the need for asynchronous intellectual property (IP) blocks to interact with each other. These aspects prevent the instantaneous capture of a complete and consistent state of the SOC, and make the SOC non-deterministic at both...

article

Modeling the interaction of gametes and embryos with the maternal genital tract: From in vivo to in silico

A. Van Soom, L. Vandaele, L.J. Peelman, K. Goossens, more

Theriogenology > 2010 > 73 > 6 > 828-837

Understanding the complex interaction between gametes or embryos and the maternal genital tract requires the use of experimental models. The selection of the right model is an important task to undertake, and despite many new developments in this area, an ideal model system has not yet been developed. In this review article, we focus on how the most appropriate model species and model system can be...

chapter

3-tier reconfiguration model For FPGAs using Hardwired Network on Chip

M.A. Wahlah, K. Goossens

2009 International Conference on Field-Programmable Technology > 504 - 509

2009 International Conference on Field-Programmable Technology (FPT 2009)

We envision that future field-programmable gate arrays (FPGAs) will use a hardwired network on chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a 3-tier reconfiguration model that uses the HWNoC as the underlying platform to realize dynamic loading, starting, and stopping of applications...

chapter

Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip

M.A. Wahlah, K. Goossens

2009 International Conference on Reconfigurable Computing and FPGAs > 380 - 385

2009 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009)

We envision that future FPGA will use a hardwired network on chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a reconfiguration methodology which makes use of such a platform to realize composable inter-application communication and persistent-state intra-application when run-time partial...

chapter

Efficient Multicast Support in Buffered Crossbars using Networks on Chip

I.V. Senin, L. Mhamdi, K. Goossens

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference > 1 - 7

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

The Internet growth coupled with the variety of its services is creating an increasing need for multicast traffic support by backbone routers and packet switches. Recently, buffered crossbar (CICQ) switches have shown high potential in efficiently handling multicast traffic. However, they were unable to deliver optimal performance despite their expensive and complex crossbar fabric. This paper proposes...

chapter

Dynamic workload peak detection for slack management

A. Milutinovic, K. Goossens, G.J.M. Smit

2009 International Symposium on System-on-Chip > 42 - 47

2009 International Symposium on System-on-Chip - SOC 2009

In this paper an analytical study on dynamism and possibilities on slack exploitation by dynamic power management is presented. We introduce a specific workload decomposition method for work required for (streaming) application processing data tokens (e.g. video frames) with work behaviour patterns as a mix of periodic and aperiodic patterns. It offers efficient and computationally light method for...

chapter

Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors

A. Molnos, K. Goossens

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools > 409 - 418

2009 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009)

Voltage-frequency scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tasks of an application. The impact of VFS on the end-to-end application performance is difficult to predict, especially when these tasks are mapped on multiple processors that are scaled independently. This is a problem for...

chapter

Composable Resource Sharing Based on Latency-Rate Servers

B. Akesson, A. Hansson, K. Goossens

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools > 547 - 555

2009 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009)

Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification complexity increases exponentially with the number of applications and must be repeated if an application is added, removed, or modified. Predictable systems offering lower bounds on performance have been proposed to manage the increasing...

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INFONA - science communication portal

Search results for: K. Goossens

The effect of maize silage type on the performances and methane emission of dairy cattle

Reduction of Mycobacterium avium ssp. paratuberculosis in colostrum: Development and validation of 2 methods, one based on curdling and one based on centrifugation

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

The Importance of Adequate Fixation for Immunofluorescent Staining of Bovine Embryos

A TDM slot allocation flow based on multipath routing in NoCs

Interactive Debug of SoCs with Multiple Clocks

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

Optimal scheduling of switched FlexRay networks

Architectures and modeling of predictable memory controllers for improved system integration

Conservative application-level performance analysis through simulation of MPSoCs

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

Modeling the interaction of gametes and embryos with the maternal genital tract: From in vivo to in silico

3-tier reconfiguration model For FPGAs using Hardwired Network on Chip

Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip

Efficient Multicast Support in Buffered Crossbars using Networks on Chip

Dynamic workload peak detection for slack management

Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors

Composable Resource Sharing Based on Latency-Rate Servers

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