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Nanoscale integrated circuits suffer both from high defect densities and increased parameter variations possibly affecting the overall timing behaviour. Components with a higher vulnerability to process variations are not just critical during test design and test application, but also during normal operation. In particular, ageing effects and changes in the operation environment including supply voltage,...
In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level...
With the advent of VLSI, very complex circuits can be implemented in a single chip. So the need for testing the chip increases with the integration. Fault diagnosis results in improving the circuit design process, the manufacturing yield, cost of testing and also reduces the time to market. Diagnosis of today's complex faults is a challenging problem due to the explosion of the underlying solution...
Quasi-Delay-Insensitive (QDI) asynchronous circuit are known as a category of asynchronous circuits that are intrinsically robust toward timing variation. QDI circuit can be sound engineered using template-based design methodology and only under isochronic fork timing assumptions. Hence, generation and verification of these timing constraints are necessary steps in practical designs of QDI circuits...
Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic...
A compact model is presented which realistically reproduces TFET characteristics and allows complex circuit simulation and parameter optimization studies. The model has been applied to circuit simulations which reveal anomalous switching behavior, and to a multi-parameter optimization study which quantifies the power-performance advantage of the TFET over conventional MOSFETs.
The ultimate goal of this work is to identify a methodical analysis of imager design to achieve high level of flexibility and modularity. It will enable early stages of design space exploration using hierarchical approach. In particular, we develop generic models for imager IC in order to explore early design choices throughout the hierarchy. This modeling approach supports top-down design flows.
In this paper a waveform relaxation algorithm based on longitudinal partitioning is presented to efficiently model large distributed networks. The proposed methodology represents lossy transmission lines as a cascade of lumped circuit elements and lossless line segments, where the lossless line segments are modeled using the method of characteristics. This allows the transmission line to be naturally...
We propose a novel model order reduction technique that is able to accurately reduce electrically large systems with delay elements, which can be described by means of neutral delayed differential equations. It is based on an adaptive multipoint expansion and model order reduction of equivalent first order systems. The neutral delayed differential formulation is preserved in the reduced model. Pertinent...
There are many test challenges generated from at-speed delay testing requirements. BIST circuit can help to solve traditionally slower AT E tester problems. In this paper, a double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency,...
Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient...
A formulation and implementation of the III–V FET nonlinear charge model decomposed into a combination of univariate voltage depletion charges and a bivariate mixed voltage-current dependent “drift” charge is presented. The concept is based on the principles used in well-established BJT models where depletion and diffusion charges are modeled separately. Analogous to the diffusion charge in BJT models,...
GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on-chip interconnects as RC, and RLC circuits. In this paper a platform to generate the T and Π configurations for RC, RLC and RLCG models based on GAM, TPN and AWE methods is proposed. With the Π configuration of AWE-based RLC model provides the best performance, this model has been mapped to an equivalent simple...
We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.
Simulations of an inverter and a 32-bit SRAM bit slice are performed based on an atomistic approach. The circuits' devices are populated with individual defects, which have realistic carrier-capture and emission behaviour. The wide distribution of defect time scales, accounts for both fast (Random Telegraph Noise - RTN) and near-permanent (Bias Temperature Instability - BTI) defects. The atomistic...
Power supply noise is very important in delay testing. Excessive noise can cause circuit delay increases that lead to test overkill. Test patterns that are too quiet can lead to test escapes. In this work, we introduce a realistic low cost delay test compaction flow that guardbands circuit delay during test using a sequence of estimation metrics. Significant reductions in CPU time are demonstrated...
Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been developed for screening SDDs, but they suffer...
In sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error results into an unacceptable chip failure rate. A method to estimate the probability of SET propagation to the output gate at any time instant within the latching window is proposed. Its accuracy is evaluated using Monte Carlo simulations.
We present an implementation of a programmable axonal propagation delay circuit which uses one first-order log-domain low-pass filter. Delays may be programmed in the 5–50ms range. It is designed to be a building block for time-delay spiking neural networks. It consists of a leaky-integrate-and-fire core, a spike generator circuit, and a delay adaptation circuit.
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