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The following topics are dealt with: post-silicon debug and customer returns; 3D integrated circuit; power issues in test; analog, mixed-signal and RF test/diagnosis; on-chip parametric sensor; delay and performance test; multifaceted approaches for field reliability; advanced methods for leveraging new test standards; memory test and repair; low power integrated circuit test; on-line and system testing;...
Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for...
With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools....
Post-silicon validation and debug have gained importance in recent years to track down errors that have escaped the pre-silicon phase. Limited observability of internal signals during post-silicon debug necessitates the storage of signal states in real time. Trace buffers are used to store these states. To increase the debug observation window, it is essential to compress these trace signals, so that...
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test...
Pre-bond testing of 3D ICs improves yield by preventing bad dies and/or wafers from being used in the final 3D stack. However, pre-bond testing is challenging because it requires special scan chains and power delivery mechanism. Any 3D scan chains that traverse multiple dies will be fragmentized in each individual die during pre-bond testing. In this paper we study the scan chain and power delivery...
Three-dimensional Stacked Integrated Circuit packages interconnected using high speed Through-Silicon Via technology can be efficiently manufactured using a wafer-to-wafer stacking process. Efforts to mitigate degradation in the composite yield of the stacked die are primarily focused on matching defect maps while assigning the pre-tested wafers from the available wafer repository to individual wafer...
Test, validation and characterization of high-speed circuits is a becoming a complex issue due to increase in circuit marginality, higher fallout, and more complex test solutions. The issue is compounded by the complex interactions between packaged components; interconnect design and customer board designs. This session will address the challenges in characterizing high-speed circuits including PLLs...
Transitions embedded in between consecutive stimulus/response bits toggle scan cells during shift operations. The consequent switching activity in the scan chains further propagate into the combinational logic, resulting in elevated power dissipation levels, and thus, endangering the reliability of the chip being tested. Based on the observation that the content of scan chains during shift operations...
In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be used to profile leakage power consumed by the...
Power supply noise is very important in delay testing. Excessive noise can cause circuit delay increases that lead to test overkill. Test patterns that are too quiet can lead to test escapes. In this work, we introduce a realistic low cost delay test compaction flow that guardbands circuit delay during test using a sequence of estimation metrics. Significant reductions in CPU time are demonstrated...
Low cost diagnosis of RF systems has become an important problem due to increased process variability effects on the performance of RF devices and the need to ramp-up RF IC yield rapidly. In the recent past, there has been work on diagnosing RF device model parameters from random “frequency-rich” test stimulus. In this paper, we develop a novel test stimulus generation approach which produces a compact,...
Parametric fault testing of non-linear analog circuits based on a new mathematical transform is presented. The V-Transform acts on the polynomial expansion of the circuit's function. Its main properties are: 1) to make the polynomial coefficients monotonic, 2) to reduce masking of parametric faults due to process variation, and 3) to increase the sensitivity of polynomial coefficients to the circuit...
Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise...
Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been developed for screening SDDs, but they suffer...
Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This paper describes a static test compaction procedure for such mixed test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Experimental...
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