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As semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a technique to mitigate its impact on circuit delays. First, we model NBTI impact on a gate while considering both the degradation of its own transistors...
Aggressive technology scaling has resulted in stability reduction for classic SRAM designs. This is especially problematic for large integrated circuits. The stability of SRAM cells can be affected by noise during a read operation and by radiation during the standby mode. In this paper, we present an approach to address the gradual stability reduction in SRAM designs. We present an SRAM design tradeoffs...
Driven by strong economic incentives the globalization of the semiconductor design and fabrication industries has given rise to numerous vulnerabilities in the manufacturing chain. From design to production countless hands contribute until fabrication is completed. An adversary can introduce a Trojan designed to disable and/or destroy a system at some future time or the Trojan may leak confidential...
In this paper a soft error correction scheme for embedded storage elements in level sensitive designs is presented. It employs space redundancy to detect and locate Single Event Upsets (SEUs). It is able to detect SEUs in registers and employ architectural replay to perform correction with low additional hardware overhead. Together with the proposed bit flipping latch an online correction can be implemented...
Since the discovery that hardware used for cryptographic applications could leak secret information through its power or radiation profile a wide range of possible attack methods has been published. The rapid evolution of these side-channel attacks made it increasingly important to minimize this possible information leakage. Additionally timing information also derived from this power profile is used...
Modern microcontroller devices for automotive applications are highly safety critical, and so are their embedded memories. It is necessary to ensure the memories to be fail safe during life time. Hence, the detection of latent faults is a big issue in memory testing, as these faults may remain during life time, but need to be detected early in production. Burn-In makes such faults detectable as they...
Increases in the powerful features being deployed through the JTAG interface has left the testing platform vulnerable to malicious users. In this paper the hardware implementation of a flexible multilevel security access system is described. The security mechanism allows for higher granularity for controlling user access of individual scan chains. This allows for blocking of individual opcodes from...
Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR...
We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.
In the near future the automotive systems will include microcontrollers hosting homogeneous or heterogeneous multi-core architectures, in which two or more CPU cores are combined to satisfy the high performance requirements. For those devices, time dependability issues represent a key challenge. In addition to that, they shall satisfy standards like ISO 26262 for functional safety and AUTOSAR for...
Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by means of an ad-hoc HW module connected to the address, data and control buses of the microprocessor. This module behaves as a peripheral towards...
Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with...
Soft errors are one of the biggest reliability challenges for present day electronic devices. With technology scaling, the contribution of soft errors to overall device failure is on the rise and it is becoming the dominant reliability failure mechanism. Several techniques exist for the detection and correction of soft errors. Reducing implementation overhead is one of the areas which researchers...
Memory blocks are important features of any design, in terms of functionality, silicon area and reliability. Embedded SRAM instances are critical contributors to the overall Soft Error Rate of the system, requiring a careful consideration of the reliability aspects and adequate sizing of the error mitigation capabilities. While error detecting and correcting codes are widely available and particularly...
Recent literature shows that the performance of a bus with crosstalk is improved using a multi-threshold capture mechanism with the trade-off on the noise margin. This work proposes a method to generate error correction code suitable for multi-threshold receivers to circumvent the noise margin trade-off. The overhead of the proposed technique is significantly less than existing encoding techniques...
We present a new reliable high-performance interconnection approach destined for complex System on Chip based on the network-centric approach. The originality of our approach is to avoid the lost of data packets, detect routing errors and reduce data packets latency by emptying output buffer when the neighbour router is unavailable. We present the basic concepts of the reliability communication technique...
In wireless multimedia systems, significant power is consumed in processing image/video content This research looks specifically at the energy cost of wireless image/video transport focusing on image quality as an end metric. The quality of received image/video content depends on the effective bit error rate of the communication channel and the amount by which the image/video data is compressed prior...
This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones,...
Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally...
Reliability and manufacturability have emerged as dominant concerns for today's multi-billion transistor chips. In this paper, we investigate how to degrade a chip multiprocessor (CMP) gracefully in presence of faults, by keeping its architected functionality intact at the expense of some loss of performance. The proposed solution involves sharing critical execution resources among cores to survive...
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