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Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internet-based applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial...
Contemporary digital systems must be based on the “System-on-Chip — SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper — AW) constitutes a major drawback for this kind of devices...
In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wave-pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks...
Mapping into K-input lookup tables (K-LUTs) is an important step in synthesis for Field-Programmable Gate Arrays (FPGAs). The traditional FPGA architecture assumes all interconnects between individual LUTs are “routable”. This paper proposes a modified FPGA architecture which allows for direct (non-routable) connections between adjacent LUTs. As a result, delay can be reduced but area may increase...
Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into...
Existing literature documents a number of techniques for combining a set of independent datapath designs into a single datapath that is run-time configurable to the functionality of any datapath in the set. This paper explores how delay, energy and area overhead attributable to reconfigurability scales with the number of configurable functionalities, independent of the design of specific datapaths...
The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this...
One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FPGAs. Replication is implemented for circuit input...
Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices...
Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency...
The design and implementation on an FPGA of a correlation system for the American and Russian Global Positioning Systems (GPS and GLONASS) receivers are presented in this paper. This system permits processing the received signal asynchronously with the data-bits. Typically, in GPS and GLONASS receivers, correlation channels receive the samples in intermediate frequency signal, process them through...
This paper presents a high speed architecture for composite field arithmetic based SubBytes transformation (S-box) used in Advanced Encryption Standard (AES) encryption. The proposed architecture is derived by extending the pre-computation technique suggested recently by Liu and Parhi to a recently proposed architecture of AES S-box due to Rashmi, Mohan and Anami. The proposed design of S-box is shown...
In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently...
The wire segmentation scheme, the ratio of each wire segment element, and the routing switch type, all as routing resources play an important role in the overall performance of FPGAs. This paper presents a smart comprehensive approach to achieve an efficient wire segmentation scheme, and a proper routing switch style for optimum performance of FPGAs in terms of output signal features such as delay,...
This paper describes the design of an auto-associative memory based on a spiking neural network (SNN). The architecture is able to effectively utilize the massive interconnect resources available in FPGA architectures as a good match to the axons in biological neural networks. A complete implementation of the memory on a single FPGA is presented. The signal processing circuitry is composed from simple,...
FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding...
The satisfiability (SAT) problem is to find an assignment of binary values to the variables which satisfy a given clausal normal form (CNF). Many practical application problems can be transformed to SAT problems, and many SAT solvers have been developed. SAT problem is, however, NP-complete and its computational cost is very high. In order to reduce the computational cost, preprocessors are widely...
This paper presents Hydrate (HYbriD Reconfigurable ArchiTecture Expressions), a generic architecture description language for exploring hybrid FPGA designs. Hydrate is based on the XML architecture description for the VPR tool. These expressions consist of variable, repeat and conditional statements to allow flexible, reusable and readable description for FPGA architectures, without modifying the...
This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance...
This paper describes the design and implementation of low power arithmetic circuits for digital signal processing (DSP) applications, using Xilinx XC5VLX30 (Virtex-5) field programmable gate array (FPGA) devices. DSP is a highly demanding application domain in the present day technology wherein the demands for enhanced performance and reduced resource utilization have increased over the years. Recent...
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