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At the cutting edge of todays embedded technology FPGA platforms are increasingly utilized for security sensitive applications. Besides the strength of cryptographic IP-cores on FPGAs the reconfiguration process of these modules has to be aware of both, algorithmic and implementation attacks in order to prevent unauthorized usage and counterfeiting. Due to the fact that most resources on the FPGA-based...
The extensive use of Systems-on-Programmable-Chips (SoPCs) in many application domains emphasizes the importance of analysing the vulnerability of the designs to single-event upsets (SEUs) and proposing efficient low-cost mitigation approaches. Most SEU mitigation approaches proposed so far in the literature for SoPCs are based on the use of popular hardware redundant techniques combined with memory...
This paper describes the design of an auto-associative memory based on a spiking neural network (SNN). The architecture is able to effectively utilize the massive interconnect resources available in FPGA architectures as a good match to the axons in biological neural networks. A complete implementation of the memory on a single FPGA is presented. The signal processing circuitry is composed from simple,...
FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding...
We present preliminary results towards realization of three dimensional material implication logic with monolithically stacked TiO2-based memristive devices. As a first step towards our goal we have fabricated and successfully demonstrated resistive switching for top and bottom layer memristors of the bilayer device stack. The 3D aspect of the circuits, which is a main novelty of our work, enables...
We present Constant Power Reconfigurable Computing, a general and device-independent framework based on a closed-loop control system used to keep the power consumption constant for any reconfigurable computing design targeting FPGA implementation. We develop an on-chip power consumer, an on-chip power monitor and a proportional-integral-derivative controller with circuit primitives available in most...
The satisfiability (SAT) problem is to find an assignment of binary values to the variables which satisfy a given clausal normal form (CNF). Many practical application problems can be transformed to SAT problems, and many SAT solvers have been developed. SAT problem is, however, NP-complete and its computational cost is very high. In order to reduce the computational cost, preprocessors are widely...
While partial reconfiguration on FPGAs has attracted significant research interest in recent years, designing systems that leverage it remains a specialist skill. Systems with a large number of reconfigurable modules can be challenging to design. Deciding on how many reconfigurable regions to use is not always straightforward, yet this choice impacts area efficiency and configuration latency. Current...
Loop pipelining is a key transformation in high-level synthesis tools as it helps maximizing both computational throughput and hardware utilization. Nevertheless, it somewhat looses its efficiency when dealing with small trip-count inner loops, as the pipeline latency overhead quickly limits its efficiency. Even if it is possible to overcome this limitation by pipelining the execution of a whole loop...
The π-calculus is a process algebra originally designed for modelling communicating systems. In this work, it is applied to the design of schedules for partial dynamic reconfiguration, which denote when modules become active and which channels they use for communication. While the execution of the π-calculus in software is possible, a direct execution in hardware is desirable for two reasons: Firstly,...
With ever increasing network speed, scalable and reliable detection of network port scans has become a major challenge. In this paper, we present a scalable and flexible architecture and a novel algorithm, to detect and block port scans in real time. The proposed architecture detects fast scanners as well as stealth scanners having large inter-probe periods. FPGA implementation of the proposed system...
In this paper, we describe a generic approach for integrating a dynamically reconfigurable device into a general purpose system interconnected with a high-speed link. The system can dynamically install and execute hardware instances of functions to accelerate parts of a given software code. The hardware descriptions of the functions (bitstreams) are inserted into the executable binary running on the...
Modern systems often contain special-purpose hardware for performance and power reasons. It is sometimes difficult to know a priori the best decomposition of the system from performance point of view. Since different components are designed by different teams it also difficult to ensure that the whole system would function properly when various components are put together. These risks can be mitigated...
Modern commercial Field-Programmable Gate Array (FPGA) architectures contain look-up-tables (LUTs) that can be “fractured” into two smaller LUTs. The potential of packing two LUTs into a space that could accommodate only one in traditional architectures complicates technology mapping's LUT minimization objective. Previous works introduced edge-recovery techniques and the concept of LUT balancing,...
This paper presents software and hardware co-design of an FPGA-based Connect6 solver with scalable streaming cores. The solver searches a game tree by using the miniMax algorithm with alpha-beta pruning. Since evaluation of board situations is the most time-consuming part, we adopted an approach to accelerate it with dedicated hardware while other parts are executed by software. We design a custom...
In recent years, object detection has been more frequently integrated with other vision processing functions, acting for acquisition of region of interest and is widely adopted in portable devices such as digital camera capable for automatic focusing on faces. In applications targeting those devices, limitations in both hardware resources and power supply mean an efficient utilization of hardware...
Trusted computing is gaining an increasing acceptance in the industry and finding its way to cloud computing. With this penetration, the question arises whether the concept of hard-wired security modules will cope with the increasing sophistication and security requirements of future IT systems and the ever expanding threats and violations. So far, embedding cryptographic hardware engines into the...
FPGA architecture exploration is a topic of great interest to hardware researchers. By synthesizing many hardware descriptions with different architecture specifications, it is possible to compare the generated circuits and draw a conclusion about those specifications. In order to be confident in results obtained from this exploration, it is necessary to verify that the circuits have been compiled...
Many stand-alone, FPGA-based accelerators separate the implementation of a computation into two components — (1) a large parallel component that is realized as hardware on spatial FPGA fabric and (2) a small control and co-ordination component that is realized as software on embedded soft-core processors like an off-the-shelf Xilinx Microblaze (or host offchip CPU). While this hardware-software partitioning...
Mapping applications onto a Coarse Grained Re-configurable Architecture (CGRA) requires knowledge about the interconnect topology used on the reconfigurable fabric. In order to make communication as efficient as possible, the application sub-structures or partitions need to be mapped to appropriate Compute Elements on the fabric, such that frequently communicating nodes are placed closer. In this...
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