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Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of US copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For...
Dynamic reconfiguration system allows us to dynamically allocate hardware resources as needed by particular applications. This paper focuses on the application of FPGA-based partial dynamic reconfiguration system (PDRS) with configurable boundary-scan circuit (CBSC), which can be used in many different fields, especially in the military and aerospace fields. Generally speaking, if an important function...
This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III...
B-spline curves can represent almost any smooth shape, being adopted by file exchange standards, used as a wavelet basis for multiresolution systems and manufacturing efficiency is increased using b-splines toolpaths. The respective algorithms for conventional CPUs demand great computational effort, requiring another hardware architectures, like GPUs, for better processing efficiency. This paper describes...
This paper presents a Radix-2 Single-Path Delay Feedback (R2SDF) configurable processor to calculate 64/128/512/1024/2048-point Fast Fourier Transform (FFT). Such range of FFT input sequences allows for the realization of the widely used wireless protocols IEEE 802.11n (WLAN) and the IEEE 802.16 (WiMax). The presented R2SDF configurable processor, as well as a fully sequential configurable processor...
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference...
Brazilian government has been investing in microelectronics, especially in hardware education as a strategic factor. In the literature, FPGA-based methodologies have been widely used in hardware and embedded systems design teaching. However, these methodologies don't take into account timing design constraints and an in-depth verification process, essential to understand physical issues, reduce non-recurrent...
This paper presents a dedicated architecture for the Rotational Transform (ROT), which is one of the novel tools proposed by the HEVC emergent video coding standard. The main goal of this coding tool is to achieve higher energy compaction of the main transform coefficient matrix and thus improve entropy encoding and minimize quantization error. The architecture was designed with nine pipeline stages,...
The intention of this paper is to show how the history of the electronic technology can be seen, as well as science, through revolutions. Such changes can be predicted by means of two projections: Moore's Law and Makimoto's Wave. The first one, in the present of normative nature, indicates that procedure must follow the semiconductors industry. The second one, analytical, describes the industry behavior...
A typical high-speed decoder implementation for an LDPC may require hundreds or even thousands of variable and check node processors. Since check node processing unit (CNPU) is far more complex than variable processing unit, hardware requirements of CNPU has a big impact on the final decoder complexity. Here, an FPGA implementation of the soft parity check node for min-sum LDPC decoders is analyzed...
Design of digital circuits and systems are topics covered in undergraduate courses on Computer Science, Computer Engineering, and Electrical Engineering. Simple processor architectures are used as example of digital systems to apply and integrate the concepts studied in these courses. In this paper, we discuss the use of a simple processor named BIP (Basic Instruction-set Processor) in courses on...
Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list...
This paper presents the design of an 8192-bit RSA cryptoprocessor using a radix 2 Montgomery multiplier based on a systolic architecture. In this case, the Montgomery multiplier simultaneously performs two multiplications, and the cryptoprocessor carries out the modular exponentiation using the binary exponentiation algorithm. The designs are described using generic structural VHDL and synthesized...
This paper presents an MPEG-4 AAC decoder described in VHDL language and compliant with the Brazilian Digital Television standard (SBTVD). It has been synthesized to an Altera Cyclone II 2C35 FPGA using 26549 logic elements and 248704 memory bits. The implemented architecture has been verified using an Altera DE2 prototyping board, being capable of decoding stereo signals coded as MPEG-4 AAC Low Complexity...
This paper presents a FPGA based embedded system to perform active vibration control of flexible structures. The FPGA flexibility integrates digital generation, acquisition, and the software for the control application. A single FPGA-based board with no external digital components was used to build an embedded system, providing maximum flexibility and reduced part count. Experimental setup presents...
This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA using different floating-point representation precision: single, double and 40-bits. The architectural approach is divided into five principal parts, four modules and one unit, namely Change Row Module, Pivo Module, Matrix Elimination Module, Normalization Module and finally the Gauss-Jordan Control-Circuit...
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