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Conventional flip chip technologies such as the mass reflow (MR) process and the thermal compression bonding (TCB) process are commonly used technologies in the micro assembly field. However, there is a continuous need for next generation interconnection technology to achieve a low form factor with increasing die and substrate complexities. Moreover, very thin 3D integrated packages and 2.5D packages...
Power semiconductor devices and modules need highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. Ag sintering chip-attachment has several advantages for heat dissipation. This work clarifies the thermal stress profiles under thermal cycling test by 3D multi-physics solver for double-side and single-side direct bonding structures with...
3D WLCSP using via last TSV (through silicon via) technology is an ideal packaging technology to meet small-form-factor, high I/O density, high-speed and most important, lower cost. For thin 3D WLCSP with TSVs, a number of critical processes need to be developed such as oxide etch, via cleaning and wafer de-bonding. In the present paper, processes for 8 inch, thin WLCSP with TSV diameter of 40µm and...
This paper presents buckled nitride thin-film encapsulation using anti-adhesion layer assisted transfer technique and BCB/nitride bilayer wrinkling due to elastic property mismatch between the two attached materials. A 900 nm silicon nitride film is deposited on a Si carrier wafer coated with hydrophobic monolayer and then non-patterned nitride film is directly bonded to BCB sealing rings prepared...
This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip cooling. A thermal demonstration vehicle (TDV) has been designed, fabricated and assembled. Radial micro-channels based on deep Si etching was integrated with a manifold chip to form a 2-layer chip stack, which has been assembled using a ceramic substrate and a Cu manifold. A test vehicle with an effective...
Through Silicon Via (TSV) was original proposed for the three-dimensional (3D) IC packaging and now is realized in the high band width DRAM (HBM) application. TSV is also utilized in a passive silicon interposer and the insertion of such interposer into a flip chip packaging created another packaging platform commonly known as 2.5DIC for high density multiple ICs integration. However, since the 1st...
Warpage control is a key process character for 2.5D IC without Through-Silicon Vias (TSV). For low cost package trend, TSV is not used for advanced 2.5D IC package. Yield is still an issue for 2.5D IC package, Die-Bonding (DB) last process is applied to make sure top die is bonded on good interposer. Therefore, no top die will be sacrificed for low interposer process yield, cost could be more reduced...
Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient...
Silver (Ag) solid solution with indium (In) is further studied since Ag-In binary system has been demonstrated with an extraordinary anti-tarnish property and superior mechanical properties, such as malleability, strength, and ductility. How to fabricate that kind of bonding materials at relative low temperatures is a challenge. In this paper, the unique Ag-In solid solution joints are produced successfully...
Throughput issue is limiting the adoption of 3D IC stacking process although 3D IC has many advantages in shorter communication lines, lower electrical parasitic and lower package footprint. Local thermal compression bond on each chip stack incurs enormous process time if there is a need to have multi-chip stack and it will be further complicated with the enormous number of chip stack on one 12"...
This paper reports fabrication of CMUT (Capacitive Micromachined Ultrasonic Transducer) based forward looking ultrasonic endoscope using custom designed LTCC (Low Temperature Co-fired Ceramic). Bottom electrodes and cavities are separately patterned on LTCC and SOI wafers, respectively. LTCC wafer is used as bottom substrate (prime wafer) for anodic bonding and ring array and linear array CMUTs transducers...
In this sturdy, we investigated the bonding and debonding of the glass wafers using Surface Activated Bonding (SAB) method with the Si and Fe intermediate layers. In the fabrication process of the Thin Film Transistors (TFTs) on the ultra thin glass substrates for the display devices, the glass substrates are handled at high temperature and can be easily deformed. In order to achieve the accurate...
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass...
Room temperature bonding of Polymethylglutarimide was performed for a damage-free layer transfer method. The PMGI layer was bonded to support Si wafer by using the Surface activated bonding method using nano-adhesion layers. Using SAB, bonded area covering around 90% of the wafer surface, with a room temperature bond strength of ∼1 J/m2 is achieved. Micro voids at bond interface are never observed...
Back-via three-dimensional (3D) integration using multiple thin-wafer transfer processes has been developed at GINTI, Tohoku University, where visible laser was employed for wafer debonding. The potential advantages of laser debonding are (i) the realization of ultra-thin wafer releasing with less stress as compared to the conventional thermal and chemical debonding methods, and (ii) no adhesive residues...
We report the results of heat transfer analysis of CoW (chip on wafer) process in which IC chips are bonded on a Si wafer by using thermal compression bonding (TCB). The throughput can be remarkably improved because a lot of chips can be pre bonded on a wafer by using non-conductive film (NCF) which is pre-applied adhesive and can be thermally pressed at a time. However, to realize this process, it...
An increasing number of substrates get sent through thinning. Some of those also require a polished surface. Temporary bonding is needed to support that. In order take some Si wafers down to 15u, a process flow with unique bonding, grinding, and polishing steps was used. Understanding how to improve many of the process steps was important to achieving the objective.
This paper reports a novel, low-cost and inherently simple vertical signal transmission method for glass-silicon-glass sandwich micro-electro-mechanical systems (MEMS) gyroscopes based on heavily doped silicon-bridge. As for the fabrication technique, only glass-to-silicon anodic bonding and after-laser-trimming process are needed, which are fully compatible with standard MEMS technology. Micro gyroscopes...
Current FOWLP (Fan-Out Wafer-Level Packaging) technology, eWLB (embedded Wafer-Level Ball Grid Array), has limited heat dissipation capability, as the materials used in, namely the EMC (epoxy mold compound), originally aimed process ability and mechanical stability, but not heat conduction. As eWLB technology expands to WLSiP (Wafer-Level System-in-Package) and WLPoP (Wafer-Level Package-on-Package)...
As the size of microbumps continues to shrink, the amount of solder decreases gradually, resulting the brittleness of solder joints due to formation of intermetallic compounds. Low-temperature Cu-to-Cu direct bonding appears to be one of the solutions for fine-pitch microbumps for 3D IC packaging. However, the high bonding temperature and pressure are the main problems of this approach. We achieve...
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