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The continual downscaling of CMOS transistors, as predicted by Moore's Law, has faced tremendous challenges in terms of performance and cost reduction. Through Silicon Via (TSV) technology provides an alternative "More than Moore" solution for system level integration, resulting in smaller form factor, reduced power consumption and large bandwidth for higher data transfer rate. Via-last...
Epidermal pressure sensor that directly contacts with human skin can be used to monitor physiological signals, such as pulse, blood pressure, and heartbeat etc. Although promising stretchable substrates and electrodes were developed in the past, there is a need for a technology to produce inexpensive epidermal pressure sensor that is sensitive to a low-pressure regime and is flexible and stretchable...
In order to remove the photoresist during the rework process, a dry rework is primarily used to ash the photoresist followed by a wet cleans process to remove the remaining organic residues. An effective process with very high particle removal efficiency (PRE) is desired at this surface cleaning step. A cleans process with lower PRE leaves particles on the wafer surface which create extra pattern...
This paper demonstrates the integration of microfluidic cooling for thermally limited 3-D microsystem applications. Thermal modeling of logic and memory dice on a silicon interposer is presented under air and microfluidic cooling conditions. Moreover, the electrical characteristics of micropin-fin-embedded through silicon vias (TSVs) immersed in deionized (DI) water are investigated through high-frequency...
Backside nanotexturing fabricated by electroless metal assisted wet chemical etching, protected with a deposited thin silicon layer, is a new approach to create high bending strength silicon samples. Bending strength for protected nanotextured samples followed by CMP process was enhanced by ∼3.4 folds as compared to polished silicon samples, which emphasize the possibility of industrial implementation...
This paper presents amino-terminated micro pattern transferring onto a mica substrate using polydimethylsiloxane (PDMS) soft stamp and proteoglycan (PG) molecular immobilization. PDMS bump-arrays with ultra-smooth surface were fabricated utilizing anisotropic etched silicon substrate as a mold. Coating and removal of releasing-agents were investigated to improve detachability of PDMS stamp from silicon...
This paper describes an octopus bioinspired vacuum gripper for transportation or assembly of industrial parts. The previous gripper can grasp the object with flat, curvature, uneven, and grooved surface. However, octopus has the microstructure on suction cup, for example, cylindrical and radial grooves and micro bump. These structure is expected to improved flexibility and adhesive force of suction...
This paper presents a cost-effective method to transfer vertically aligned carbon nanotubes (VA-CNTs) with Poly(dimethylsiloxane) (PDMS). Here, in this process, we take the advantage of PDMS solution as the transfer medium, meanwhile utilize the good wetting of this solution on another cured PDMS film to realize efficient transfer. The SEM images of transferred CNTs were taken to characterize the...
To solve the low implantation rate of in-vitro fertilization (IVF), zona-free oocyte is widely used in IVF [1]. However the process of zona-removal is not only tedious but also easy to harm the fragile oocyte. In this work we introduce a 3-dimensional microfluidic device to simplify the zona-removal process, and the applied gentle process is also capable to keep oocyte intact and precisely locate...
This paper presents observation of oscillations in TWT simulations at a frequency close to the band edge frequency when the electron beam is not well-focused and well-aligned. The cause of the oscillations is suggested to be backward-wave oscillations.
Micro electro mechanical systems (MEMS) based micro gripper for micro-assembling processes is designed. Gripper arms are actuated using a combination of Ni-Ti shape memory alloys and Si springs allowing a gripping range of 1–120µm. Heat which is needed to actuate shape memory alloy (SMA) is obtained by electro thermal properties of Ni-Ti by passing a current which is controlled by specially designed...
This paper is on a vertical through silicon via (TSV) fabrication method of integrated circuit (IC) packages. The vertical TSV processes are developed by evaluating different via depth and diameter. The stress simulation and analysis of the as-formed vertical TSV structure are also conducted to predict the possible mechanical failure during the reliability test.
In this paper we report an improved three-step wet etching method to achieve individual nanopore and nanopore arrays at wafer scale. Nanopore arrays and individual nanopores with feature size down to 14nm were obtained. To improve the precise control of the pore-opening point, we used a home-made device to monitor the traversing current, which presents pore-opening event. The uniformity of the nanopore...
This paper reports a tri-fold inertial measurement unit (IMU) that is fabricated with a batch-mode 3-D assembly process. Each chip of a tri-fold die includes a single axis z-gyroscope and 0–2 lateral-accelerometers. The tri-fold dies are batch-mounted on sidewalls of silicon cavities on a wafer to form 6-axis IMUs. The accelerometer has a measured bias instability of 6.8 µg and a noise floor of 66...
This paper presents an optimized design of Radio Frequency (RF) Micro-Electro-Mechanical System (MEMS) capacitive switch. The optimized design of proposed switch include utilization of three fabrication steps of lithography which helps in effectively reducing the cost of fabrication and the mechanical modeling of switch has Nano-scaled dimensions which again is beneficial in obtaining scaled device...
The filling process of Through-Silicon Via (TSV) based on printed silver using the Aerosol Jet™ method is presented and discussed. TSVs with different diameters as via-last process in 18 μm ultra-thin ChipFilm™ dies, including a self-aligned etching process and their passivation are demonstrated. Daisy chain test structures on top of ChipFilm™ dies and on the bottom wafer are used for demonstration...
The globalization of the semiconductor foundry business poses grave risks in terms of intellectual property (IP) protection, especially for critical applications. Over the past few years, several techniques have been proposed that allow manufacturing of ICs at untrusted foundries by obfuscating and/or locking, albeit at high design overhead, low security guarantees and high cost. In this paper, for...
Photonic BiCMOS is a novel technology for fabricating electronic-photonic integrated circuits. Broadband silicon photonics devices such as germanium photodiodes and depletion type Mach-Zehnder modulators were monolithically integrated in a high performance SiGe BiCMOS baseline process. Integration aspects and examples of demonstrator circuits shall be reviewed.
With the semiconductor development, more and more different devices need be integrated to achieve faster and more functionalities. Micro-bump is an important connection from chip to chip, chip to wafer and chip to substrate. We evaluated micro-bump barrier layer Ti thicknesses (400Å, 1KÅ and 2KÅ) effect on shear strength and bump chain resistance in this study.
In this paper, four types of silicon based THz dielectric waveguide are introduced. The silicon based THz dielectric waveguides are all fabricated by DRIE technology. The losses of these dielectric waveguides are very low.
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