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We propose to measure the THz surface plasmon signal transmitted after a long distance propagation over a conductive sample in view of determining the THz properties of the sample material. We demonstrate this very sensitive method on a highly-doped silicon samples. The surface permittivity differs from the Drude model prediction.
We perform optical pump-THz probe measurements in four types of silicon samples to investigate carrier multiplication. We evaluate the number of carriers from the transient change of transmission after photoexcitad carriers are thermalized to the bottom of the conduction band to discuss the possibility of carrier multiplication.
This paper presents an analysis of three types of antennas for backscatter radio reader and a method for measuring backscattering signal from antennas which involves using a network analyzer connected to an anechoic chamber with and without the receiving antenna. We analyzed the backscattered signals of two types of dipole: wire dipole at the operating frequency 1.8 GHz and microstrip dipole operating...
We have investigated characteristics uniformity of Si-wire waveguide devices formed on 300 mm SOI wafers by using ArF immersion lithography process. Very low dispersion of group indices within wafers was confirmed from measurements of asymmetric Mach-Zhender interferometers.
We present top-illumination type 100% Ge-on-Si photodetector, which achieved high-performance level ready for various optical network applications. We also present a Ge waveguide photodetector operating over 50Gb/s with high responsivity.
Stacked chip packaging (3D packaging) is an effective method to increase the density of electronic packaging, due to the packaging density on an single chip has reached the limit of current packaging process. In stacked chip packaging system, additional chips are implemented on a single chip in the third dimension, thus multiply enhance the density of electronic packaging, while the packaging size...
Self assembled Cu3Si nanoislands and nanowires on Si(110) were fabricated with electron beam evaporation in ultra high vacuum while annealing the substrate at 600 ° C. Scanning tunneling microscopy technique was used to study the resultant nanostructures of sub 10 nm size. Surface images of a nanoisland and nanowire were obtained. The former showed evidence of single crystalline structures. The length,...
This work presents CMOS on-chip antennas for wireless chip-to-chip communication. In order to provide for high antenna efficiency, the antennas have been manufactured on an ultra-thin substrate with a thickness of 17.5 µm. The antennas are manufactured in the top metallization layer and are used as ground supply for the CMOS circuitry, thus requiring no dedicated chip area. Prototypes of the proposed...
Although the introduction of nanostructures into thermoelectric materials is one of key technology for enhancement in thermoelectric conversion efficiency, a technique for characterizing the nanometer-scale materials is required. With the aim of evaluating Seebeck coefficient of nanostructured thermoelectric materials, we propose a new technique by Kelvin- probe force microscopy (KFM) which gives...
The studies of the low frequency noise in graphene transistors with the number of carbon layers from N=1 (single layer graphene) to N=15 showed that 1/f noise becomes dominated by the volume noise when the thickness exceeds approximately 7 atomic layers. We compare these results with the data on surface and volume noise in carbon nanotubes and Si MOS.
In this work, a new method for the calculation of Hall factors is described. It is based on the interdependence with mobility components via the respective relaxation (scattering) times. The new method allows an accurate determination of mobility and carrier sheet concentration from Hall-effect measurements and can not only be applied to homogeneously doped substrates but also at the interfaces of...
Along with the development of the Si semiconductor industry, numerous studies have been carried out on the defects that remain after ion-implantation processes [1]. For example, in the case of high-dose (∼1015 cm−2) implantation, dislocation loops can be created even after annealing. These defects are typically evaluated by transmission electron microscopy (TEM) and have been confirmed as a reason...
A three-dimensional (3-D) LSI has many lots of through-Si vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first...
A novel self-alignment technology, called positive self-alignment structures (PSAS), for heterogeneous 3D integration is described. Using a set of precisely reflowed photoresist structures in conjunction with the corresponding inverse pyramid pits, we demonstrate that submicron alignment can be achieved without an advanced placement tool. The positive self-alignment structure technology is fabricated...
The mounting issues of decreased yield and reliability from nanoscale integrated circuit (IC) processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes and are a major concern to...
The heat transfer in silicon microchannels with integrated inline and staggered pin fin arrays is evaluated at clearance-to-diameter ratios of 0.5 – 0.77 in the laminar flow regime. The channels have a small width, leading to a significant influence of the channel walls on fluid flow and heat transfer. Their influence is considered when measuring the temperature distribution along the channel length...
This paper presents the effect SOI detector's bias voltage has on current-voltage characteristics of different types of transistors (core transistors, io transistors, body floating, sourcetie, body-tie, low/normal/high threshold voltage). Methods of minimizing this effect were presented. Also, the I–V characteristic of transistors utilizing shielding layer (BPW - buried P Well) were measured and presented...
An infrared sensor based on a vertically integrated double layer (VIDL) thermopile which comprises of 96 thermocouples on a suspended membrane has been designed and fabricated by a CMOS-compatible process. The properties of this thermopile are characterized. The responsivity (Rs) of the VIDL thermopile is 202.8V/W and the detectivity (D∗) of it is 2.85×108 cmHz1/2 W−1.
We report the first phase-resolved measurements of nonlinear pulse propagation in silicon photonic devices. These demonstrations indicate soliton-like behavior, despite the presence of two-photon absorption (TPA) and free-carriers impacting the dynamics at 1.55 μm.
In this paper, we investigate a bit-error rate (BER) of an optoelectronic integrated circuit (OEIC) receiver. For this investigation, signal and noise characteristics of a Si avalanche photodetector and a high-speed electronic circuit are analyzed. Using the fabricated OEIC receiver, 12.5-Gb/s 231−1 pseudo-random binary sequence optical signal is successfully detected with BER less than 10−12 at incident...
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