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Based on the parabolic potential approach (PPA) and equivalent number of gates (ENG), a new quasi-3-D subthreshold current/swing model for the fully depleted quadruple-Gate (FDQG) MOSFET is developed. The model explicitly shows how the channel length, gate oxide thickness, and silicon film thickness affect the subthreshold current/swing behavior. The model is verified by its calculated results matching...
Three GaN-based buck switching power stage architectures are implemented using discrete GaN High Electron Mobility (HEMTs) devices and compared with respect to efficiency, switching speed (2 to 10MHz), and power conversion ratio for medium-power applications. The three presented power stage architectures are: a single-stage buck, a multi-phase buck with 2 phases, and a stacked interleaved configuration...
This paper presents the project procedure to develop a Half-Bridge (HB) Non-Isolated DC-DC converter applying a Normally-On GaN-based switch. Normally-on devices (D-mode) present the benefit of lower costs in terms of production if compared with E-mode devices, which gives an economic motivation to study and develop power electronics converters applying this technology. The devices under test (DUTs)...
In this paper, an all-optical logic gate with multiple functions and asymmetric structure is theoretically designed and simulated using a silicon on insulator (SOI)-based multimode interference (MMI) coupler. By switching the optical signal to different input waveguide ports, the device can function as an OR, NOT, NAND, or NOR gate simultaneously or individually. Simulation results by using three-dimensional...
In this work, we demonstrate a way to modulate threshold voltage of InGaAs Fin-structured High-electron-mobility transistors (Fin-HEMTs) by narrowing fin width of the devices. Normally-off InGaAs FinHEMT has been successfully achieved when fin width of devices is smaller than around 180 nm. Also, we introduce a theory to explain side wall gates control of FinHEMTs to modulate threshold voltage.
The superior electrical and thermal properties of silicon carbide (SiC), when compared to silicon (Si), has lead to it being used in power converter designs that require high efficiency and low volume. However while choosing the semi-conductor material for these high performance designs is relatively simple, the specific type of SiC device (e.g. JFET, MOSFET or BJT) is not so straight-forward. This...
Gallium Nitride (GaN) based devices on Silicon (Si) substrates (GaN-on-Si) promise unmatched performance at low cost. Despite this theoretical promise, the lattice and thermal conductivity mismatch between the GaN and Si has obstructed the realization of reliable electrically graded high voltage devices. Recently, a small number of manufacturers have claimed the successful development of such devices...
In this paper, key aspects of silicon-carbide (SiC)-based automotive traction drives are reviewed. Firstly, the required supporting factors to achieve optimal operating conditions and best performance are described. Major component sizing methodologies and constraints are included. Expectations on gate threshold voltage, trans-conductance, and transient oscillation are discussed. Tolerance against...
The U.S. Army Research Laboratory (ARL) and Wolfspeed developed silicon carbide (SiC) vertical MOSFETs for linear-mode operation. The motivation is to determine whether SiC's material properties enable SiC MOSFETs to withstand higher pulse-current density and energy dissipation than is achievable with commercial silicon linear-mode MOSFETs. The SiC device is a 3.3 mm × 3.3 mm chip with a thick gate...
Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer...
In this work, we provide early insight into the combined tradespace for both power switching and RF applications afforded by the high critical, electric-field strength of β-Ga2O3. MOSFETs formed by homoepitaxial growth of β-Ga2O3 films doped with Sn, Si, and Ge on bulk substrates have been characterized electrically. Several key milestones have been achieved such as enhancement-mode operation >...
CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V/Ge channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to...
In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled...
This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs. We evaluate HexFET as a potential successor to FinFET for 5nm node logic and SRAM applications using first principles atomistic-based modeling, calibrated...
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the...
In this paper, a compact model for the gate current in HKMG nMOS transistors is presented. The carrier transport through the multi-stack gate dielectrics of HKMG MOS transistors is shown to be dominated by the Trap Assisted Tunneling and Poole-Frenkel conduction mechanisms. Both these mechanisms occur simultaneously and each is dominant in a particular gate voltage range. The interdependence and simultaneity...
This paper reports the epitaxial-Si growth and dopant diffusion characteristics during fabrication of a vertical thin poly-Si channel (VTPC) transfer gate (TG) structured pixel, which is a possible candidate for future three-dimensional (3D) CMOS image sensor (CIS). Due to the increasing demand for higher resolution sensor, major CIS companies have presented various innovative 3D pixel structures...
This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
3D Finite Element ensemble Monte Carlo simulations with integrated 2D Schrödinger Equation quantum corrections are employed to forecast the performance of scaled Si gate-all-around (GAA) nanowire (NW) FETs with unstrained/strained channel. The results from the 3D MC toolbox were compared against experimental I-V characteristics of a 22 nm gate length GAA NW FET with excellent agreement. The NW FET...
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