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In this paper, a compact model for the gate current in HKMG nMOS transistors is presented. The carrier transport through the multi-stack gate dielectrics of HKMG MOS transistors is shown to be dominated by the Trap Assisted Tunneling and Poole-Frenkel conduction mechanisms. Both these mechanisms occur simultaneously and each is dominant in a particular gate voltage range. The interdependence and simultaneity...
In this paper, a physics-based compact model for the longitudinal and transverse stress profile in the channel of an uniaxially strained bulk MOS transistor is presented. The stress in the channel of a MOS transistor is not uniform and this nonuniform stress distribution results in higher average channel stress with reduction in the gate length. The developed model accurately predicts the average...
This paper analyzes and models the stress over layer induced threshold voltage (VT) shift observed in high-K metal gate (HKMG) nMOS transistors. It is shown that the conventional in-plane uniaxial strain based VT shift model cannot explain the large VT shift observed in HKMG MOS transistors. A VT shift model considering both the in-plane longitudinal and out-of-plane transverse stress component is...
Recently 9/7 lossy Discrete Wavelet Transform (DWT) has been extensively used for compression for JPEG images. In this paper, we have implemented different boundary treatments for lifting based 9/7 2-Dimensional (2-D) DWT. Boundary treatment plays a very important role in the reconstruction of the image.
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