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An atmosphere pressure sensor is developed using SOI (silicon on insulator) wafer based on MEMS technology. In this sensor, the device layer of SOI wafer is etched as the stress detection resistor. And the depth of pressure cavity is controlled by wet etching time. The whole chip is finished by anodic bonding with SOI wafer and pyrex 7740 glass wafer. Also, a kind of plastic packaging for pressure...
In the present work, we report the design, fabrication, packaging and testing of a micro-mixer microfluidic device in 2" diameter silicon substrate. For this purpose, long and deep (∼ 80 μm) channels in silicon were formed employing modified reactive ion etching (RIE) process. The RIE process parameters were carefully optimised for obtaining fast etch rate for creating 80 μm deep channels. Silicon...
Conjunction of silicon crystals with surface over 10 cm² with molybdenum discs by means of silver paste sintering is being discussed. It is shown that to ensure strength of joint and low thermomechanical stress selection of dependencies of pressure and temperature on time is very important. It is necessary to ensure thermal stability of multilayer metal process on jointed surfaces. Experimental elements...
3D IC integration based on through silicon vias (TSVs) is expected to provide an alternative technology that can exceed the Moore' Law because of its high packaging density, short signal path, low signal delays. Via filling of conductive materials is regarded as one of the key technologies in the TSV process flow. In this paper, conductive materials such as copper was chosen to fill the TSVs due to...
In this paper, a mechanical lock is first proposed and designed for LED silicone lens mounting. Since LED has many new applications in areas such as automobile headlight, micro-projector and local network optical communication, a potential serious issue must be solved. Due to the poor adhension between silicone and mostly materials including silicon, silicone lens may drop off from the silicon substrate...
After the first white light-emitting diodes (WLEDs) became commercially available, much attention has been paid to the development of WLEDs because of their extensive applications in solid lighting. Compared with traditional lighting, WLEDs have more advantages, such as high efficiency, long lifetime, fast response and environmental-friendliness [1-3]. It has been widely used in signals, displays...
Stacked chip packaging (3D packaging) is an effective method to increase the density of electronic packaging, due to the packaging density on an single chip has reached the limit of current packaging process. In stacked chip packaging system, additional chips are implemented on a single chip in the third dimension, thus multiply enhance the density of electronic packaging, while the packaging size...
WLCSP (wafer level chip scale package) has been well accepted within modern industry which brings not only the reduction of package size, but also good thermal performance vs. more traditional peripherally leaded packages. At the mean time, WLCSP feathers can significantly lower manufacturing costs. One of the barriers for WLCSP package to be accepted in the industry is the lack of existing and mature...
In this paper, a full channel simulation model of interposer and organic substrate is established. The TSV (through silicon via) interposer provides high-bandwidth, low-latency interconnection to accomplish higher performance and reach smaller size of the semiconductor devices. For 2.5D packaging, it's extremely necessary and pressing to estimate the electrical property and optimize the structure...
Optoelectronic packaging is a challenge for optoelectronic device and optoelectronic integration. In the packaging level, optical under fill compound, optical fiber array, micro lens, silicon carrier and substrate effects on the thermal, optical and reliability performance of optoelectronic packaging. To prepare this challenge, a wide range of analysis and expertise for integrated optoelectronics,...
In this paper, an improved chemical foaming process (CFP) for wafer-level glass cavities will be demonstrated for volume production in a clean room. First of all, suitable foaming agents transferring techniques are investigated to avoid powder pollution to the chips in a clean room. In addition, the precise controlling of the sizes of the glass cavities is studied theoretically and experimentally...
In this paper, four kinds of 3X3 TSV arrays in different forms of signals and grounds were modeled and simulated using Finite Element Method. The analysis was performed by ANSYS HFSS. The target of this research is to study the influence of TSV array pattern on signal transmission characteristic and to give a guide for the design of package level interconnect using TSV arrays. The simulation results...
A Silicon interposer with through silicon via (TSV) has become important key components of 3D integration. It is used as an intermediate carrier and a wiring device for IC components like logics, memories, sensors, and so on. Due to wiring with custom design on front and back side, a TSV interposer enables to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package...
This work describes a methodology and a test structure to evaluate next generation pre-applied underfill materials with concurrent flux capability for ultra-fine pitch solder-based interconnects. This simple test vehicle consists of Sn-solder micro-bumps with diameters less than 10 μm. The micro-bumps reflowed to form spherical balls when heated in reducing environments. The micro-bumps are used to...
In recent years, consumer electronics demand has been geared towards lightweight, high capacity, and high efficiency small form factor devices. These characteristics can be achieved by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. This structure...
In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100μm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature...
The qualifications of a 2×3 and a 7×7 embedded WLCSP power module were shared in this paper. The 2×3 module was built on a switching voltage regulator with three passive components and one embedded WLCSP (2×3 at 0.4 mm pitch). The chip to module size ratio is 18.1 percent. The 7×7 module was built on a 7×7, 0.4 mm pitch WLCSP daisy chain test chip and five passive components. The silicon to module...
During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is...
We report on the development of a test package that utilizes a passive silicon interposer with high density and high aspect ratio TSV's, each integrated with compliant flexible interconnect on one side of the interposer. As opposed to conventional approaches, where TSV interposers are populated with C4 and/or fine pitch micro bumps with multiple interfaces to reflow and permanently attach, our TSV...
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