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We propose and demonstrate the operation of single structure III–V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI...
We demonstrate the first VLSI-compatible approach for monolithic three-dimensional (3D) integration of carbon nanotube field effect transistors (CNFETs) with silicon CMOS for high-performance digital logic applications. Fine-grained monolithic 3D integration is demonstrated at the logic gate level, whereby individual logic gates are composed of both CNFETs and silicon FETs. Monolithic 3D integration...
We present the optimum design of tri-gate poly-Si nanowire transistors (NW Tr.) based on the systematic performance and variability analysis for various NW width (WNW) and thickness (TSi) down to 10nm. Ion difference between poly-Si and crystalline-Si Tr. at short L (down to 25nm) is much smaller than long L due to poly-Si defect-barrier lowering by high lateral field. Ion of poly-Si pFETs is close...
We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at...
A CMOS transmission line-to-waveguide transitions with a patch antenna for a WR3 waveguide (220–325 GHz) was designed using an electromagnetic-field simulator. The position of inserting the antenna to the waveguide and the size of the antenna were optimized to realize a low insertion loss and a wide bandwidth. As a result, an insertion loss of 0.9 dB and a 3-dB bandwidth of 120GHz were achieved.
This paper presents the challenges of integrating 70V and 45V lateral DMOS transistor modules into a 0.18um base line process. This integration is achieved with minimal impact on baseline process and circuit IP's. Multi-epitaxial stack and Deep Trench Isolation (DTI) modules assure up to 140V isolation capability between different areas in the chip.
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology...
For advance CMOS device manufacturing, HALO implant with high tilt angles (30–45°) and 4-rotational condition has become one of the critical implant steps defining device properties. However, from Ion Implanter tool hardware point of view, the rotation mechanism function is not able to be monitored or verified to be accurate. A failure to rotate will not generate any tool error on traditional implanter...
Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes: approach zero variability, reduce leakage currents and access resistances at the same time, fully exploit 3D integration at the device, elementary function, chip and system levels. New progress laws combined to the scaling down of CMOS based technology will emerge...
Power consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (Ev). It is also hard to form n+/p Ge junction by standard ion implantation due to the poor dopant activation by...
The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality...
Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator...
Silicon aging, in particular NBTI, causes many PUFs to exhibit a natural tendency of growing less reliable over time. This is inconvenient or even unacceptable for in-the-field applications. In case of SRAM PUFs it is observed that the impact of NBTI aging depends on the data stored in the SRAM. In this work, we investigate the effects of data-dependent silicon aging on SRAM PUF reliability under...
Direct wafer bonding can be a vehicle for the dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. Like for SiGe, direct wafer bonding enable the fabrication of fully depleted transistors having superior electrostatic control over the channel. Hybrid substrates can be also fabricated by direct wafer bonding with stacked ultra-thin high-mobility layers. A process flow allows...
Low-dark-current InGaAs metal-semiconductor-metal (MSM) photodetectors monolithically integrated with InP photonic-wire waveguides are fabricated on III-V CMOS photonics platform. By using the Schottky barrier enhancement layer consisting of the InP/InAlAs layers, the dark current is successfully reduced to 7nA at 1V bias.
CMOS technology ushered in the silicon VLSI era over thirty years ago. This talk reviews the history of CMOS devices and projects their future prospects. For any given technology node, CMOS performance is limited by the shortest channel length that can be made while maintaining the integrity of transistor action. The development of the MOSFET scale length theory will be tracked from the 1970s to the...
3D chip stacking refers to a vertical stack of chips in which individual chips can communicate with each other through electrical connections. 3D chip stacking has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. In true 3D chip stacking, all chips except possibly the topmost chip, contain TSVs (Through Substrate/Silicon Vias)...
Flexible electronic systems have been limited by the ability to integrate IC functionality. Traditional silicon-based ICs are not flexible, and flexible transistors are too large and too slow to approach silicon-based IC density and performance. Transferring standard silicon IC wafers to polymer substrates addresses these limitations by transforming traditional ICs into a physically flexible form...
This paper demonstrates a novel magnetic induced injection method of ferromagnetic composite to build electrically conductive through-silicon vias (TSVs). The through conductive via is filled with conductive ferromagnetic composite by attractive magnetic force. The composite is made of the mixture of silver and iron nanoparticles. SU-8 2002 is covered on the side walls of via as an insulating material...
A small autonomous device integrating MEMS, CMOS and photovoltaic (PV) cells has many attractive applications. For such a device, using light as a power source is preferable because power feeding and control signal transmitting can be done at the same time and in a remote manner. We demonstrated the remote power feeding to a MEMS actuator by light using PV cell array. In this article, we first proposed...
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