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This paper reports the use of mesoporous silica as a stationary phase support for serpentine semi-packed micro-fabricated gas chromatographic (GC) columns. Herein, polydimethylsiloxane (OV-101) is used as the stationary phase. It is demonstrated that gaseous alkane C1-C4 can be well separated by using the micro-fabricated GC columns in 2 m, rather than the 25–30 m of conventional capillary columns...
In this study, a micro-probe electrode array with independent interconnections through the substrate has been developed using LRS(Low Resistance Silicon) via and glass reflow process. The silicon vias have electrical resistance less than 2 Ω because the boron ion in the borosilicate glass wafer can diffuse into the LRS pillars during glass reflow process. The LRS wafer was etched with double DRIE...
This paper presents a universal self-aligned in situ on-chip micro tensile fracture strength tester designed for tensile strength extraction and process evaluation, which will provide, for the first time as far as the authors know, great force(above 100mN) to in situ on-chip specimen without the introduction of precise instrument, especially suitable for bulk micromachining related tests. The whole...
This paper reports the first experimental exploration of non-invasive and fast manipulation of breast cancer cells by harnessing multimode micromechanical resonators operating in biosolution. We demonstrate, for the first time, that groups of breast cancer cells are spatially manipulated into controlled microscale patterns, facilitated by the spatially abundant and diverse multimode resonances of...
This work reports the patterning of high aspect aluminum doped zinc oxide (AZO) for nanowall hollows and capacitive resonators by deep reactive ion etching (deep RIE) and atomic layer deposition (ALD). Nanowall hollows with 50 nm in thickness and 15 μm in height as well as smooth surfaces have been achieved and the aspect ratio of their height-to-width is as high as 300. Suspended AZO capacitive resonators...
We report an advanced deep-reactive-ion-etching (DRIE) process developed specifically for etching ultra-deep structures in thick (>500μΉ) silicon wafers with high aspect-ratio and straight sidewalls across a wide range of feature sizes and patterns. This is achieved by ramping critical process parameters throughout the etching duration. 600–800μm deep trenches with widths as small as 20–40μm are...
This paper reports an enhanced photocatalysis system for organic pollutants degradation, using high-aspect-ratio (HAR) Si/ITO/WO3 micropost photoelectrodes, fabricated by deep reactive ion etching (DRIE) and sputtering. Compared with traditional Titanium Dioxide (TiO2) photoelectrodes, Tungsten trioxide (WO3) coupled with Si can absorb visible light. Besides, an optimized HAR electrode configuration...
Integration of materials with a high dielectric constant into storage or gate capacitor applications requires a detailed understanding of the elemental and the phase composition behavior during calcination processes. In this work the elemental and the phase composition of Al2O3 films on silicon substrates obtained technology atomic layer deposition were studied. The investigations were performed before...
In this study, the piezoresistive pressure sensor of Si membrane was fabricated using the Si wet etching with a tetramethyl ammonium hydroxide (TMAH). Anisotropic Si etching properties of TMAH solution and sensing characteristics of the etched Si membrane were investigated. The addition of ammonium persulfate (AP) to the TMAH solution improved the flatness of etched Si surface and the undercutting...
TCAD simulation of the technological process of creating of the cathode-grid assembly, which consists of the field-emission cathode and control-grid electrodes, was performed. The process of forming and sharpening the cathode tip based on a standard batch processing silicon technology is presented. The proposed process flow allows opening self-aligned emitter areas in the grid layer without carrying...
Pillars formed by metal assisted chemical etching (MACE) process as a post process on a silicon cantilever are presented in this work. Although the cantilever is very fragile, the patterning of the pillar structures on the cantilever have been successfully demonstrated. The high aspect silicon pillar structures from 20 to 40 with smooth surfaces and vertically etched shapes on the cantilever are formed...
In this study, we investigated the plasma-induced damage in silicon trench etching. The damage was measured by detecting the dark current, which was a very small leakage current thermally generated from silicon crystal defects. The results indicated that both the amount and depth of the sidewall damage in the trenches were almost the same as those of the bottom damage. From the results of analysis...
The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two problems: (1) the notching near the bottom corners of TSVs and (2) the reaction product generated by the etchback step. To overcome these problems and increase TSV yield, we previously proposed a via-last TSV process using notchless Si etching and wet...
A micro rotor with high rotation speed is of vital importance for MEMS gas turbine engine to achieve its higher power density and transfer energy with high efficiency. In this investigation, a micro silicon rotor, which is fabricated by one-time multi-depth silicon etching method and supported by a 3-wafers bearing system, is completed to reach high rotation speed. To ensure wafer bonding quality,...
For the realization of the IoT (Internet of Things) society where the arrival is strongly predicted soon, the construction of an intelligent sensor network is important. For such a sensor network construction, the enormous numerical fusion devices that CMOS devices and MEMS sensors are integrated are essential. To develop WLCSP (Wafer Level Chip Size Packaging) technologies as high density packaging...
A method proposed to effectively hoist the power conversion efficiency (PCE) in single crystalline solar cells (SCS) is feasible. In the approach, the optimization of etched depth to reduce reflection of sunlight and the maximization of surface area of wafer to increase current absorption were performed by plasma enhanced chemical vapor deposition (PECVD). Results obtained by a standard testing equipment...
With the assistance of in-situ grown graphene on the wafers, semi-insulating 4H-SiC wafers were etched in aqueous KOH using photo-electrochemical method. The etching rate was estimated to be at about 50nm/min. By the cross-sectional scanning electron microscope (SEM) images, triangular structure in a similar size and aligned in the same direction was found on (1–100) face. Whereas on the (11–20) faces,...
Rapid Alternating Process (RAP) is a series of alternating polymer deposition and Si etch cycles, each lasting only 0.2~0.9sec to suppress sidewall scallops for through silicon via (TSV) application. This paper proposes depositing the nitrided fluorocarbon (N-CxFy) polymer as sidewall passivation film to eliminate the undercut damage of silicon substrate. RIE-lag effect is observed as shrinking the...
Thin body III-V-on-insulator (III-V-OI) structure is a promising device structure for future node transistors in CMOS technology. Typically, a direct wafer bonding (DWB) is used to fabricate III-V-OI on a Si substrate [1–3]. Donor wafers were etched out [1, 2] or separated by hydrogen implantation [3]. However, the former one is extremely costly and the latter one can induce the residual defects in...
In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and...
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