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We report an advanced deep-reactive-ion-etching (DRIE) process developed specifically for etching ultra-deep structures in thick (>500μΉ) silicon wafers with high aspect-ratio and straight sidewalls across a wide range of feature sizes and patterns. This is achieved by ramping critical process parameters throughout the etching duration. 600–800μm deep trenches with widths as small as 20–40μm are...
This paper presents the design, fabrication and preliminary characterization of a new type of multi-axis capacitive accelerometer with sub-µg resolution based on a robust CMOS-compatible 2-gap fabrication technology that can provide large proof-mass (1 mm tall, >2.33 milligram/mm2), high aspect-ratio (HAR) narrow sense gaps (<3 µm wide, >250 µm tall) and large sense/feedback electrode area...
This paper presents a two-gap CMOS-compatible technology to fabricate very tall (>500μm) 3D high aspect-ratio (HAR) silicon structures with narrow HAR sensing gaps (<5μm) to achieve high sensitivity in capacitive sensors. This technology is especially suited for forming capacitive MEMS sensor arrays and offers the following advantages: 1) hundreds or thousands of small-footprint high-sensitivity...
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