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We demonstrate the first monocrystalline germanium gate photoMOSFET integrated with silicon photonic waveguides and grating coupler. We measure a responsivity of 1.2 A/W at 1550nm with a 2×4 µm2 germanium gate.
MNOS memory hysteresis and memory window are simulated by calculation of tunneling probability via the potential barrier to the nitride conductance or valence band, or to Si nanocrystals embedded in the dielectric layers. The effect of the oxide and nitride current levels are studied. The memory hysteresis width depends strongly on the oxide current level. If the oxide current is close to the nitride...
We present observations of single event burnout in 200V Schottky diodes used in hybrid DC-DC converters. Two diode types were tested and showed varying sensitivity to heavy ions and protons.
IMOS device with the low static power consumption and the sub threshold swing is obviously superior to the traditional CMOS device. However, the single gate IMOS (SG IMOS) requires a relatively high gate voltage to cause the avalanche breakdown, and the partition structure of its channel leads to a reduction of the integration degree. This paper presents a double gate p-IMOS (DG p-IMOS). By solving...
This paper is aimed at exploring efficient approaches for the simulation of Random Telegraph Noise (RTN) in variability analysis of advanced floating gate non-volatile memories. RTN is traced back to randomly occupied localized traps located close to the Si/SiO2 interface. While the effect of traps has been investigated previously by means of time-consuming Monte Carlo simulations [1], in this work...
This paper presents a vertical silicon-on-insulator enhancement mode junction field effect transistor (SOI JFET) for a better on to off current performance. A major problem limiting the scaling of bulk silicon CMOS is the diminished improvement in on current and the increase in off current. The short channel effects associated with MOSFET are a serious limitation for the scaling. The main problem...
Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT)...
An architecture which has multi-gate or tri-gate architecture is called FinFET technology, deliver superior levels of scalability but design engineers face significant challenges in creating designs that optimize the promise of this exciting new technology. It is an attractive successor to the single gate MOSFET by merit of its superior electrostatic properties and comparative ease of manufacturability...
This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase...
The work presented in this paper focuses on the effects of high leakage current in field effect transistors and the possible ways to play down with the leakage currents. This paper combines density functional theory and non equilibrium Green's function formalism to perform atomic scale calculation of tunnel currents through SiO2, HfO2, Ta2O5ZrO2 and DY2O3 dielectrics in MOSFETs. The tunnel currents...
In future systems with relatively unreliable and unpredictable energy sources such as harvesters, the system Vdd may become non-deterministic. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Stable and known references are also difficult to obtain in this environment. This paper describes a reference-free voltage sensor...
Ultrathin PIN Detectors have been applied in radiation detection for particle identification and etc. In this paper, we present simulation research on the structure of ultrathin Si PIN detector based on bonding technology by using Sentaurus TCAD tool. The normal structure and reverse structure of ultrathin Si PIN detector are simulated and compared. The reverse current of detector and electrical field...
pMOS-RADFET (radiation field-effect transistor) as micro-dosimeter has been widely applied in spacecraft, medicine and personnel dosimetry. Thick gate-oxide and zero threshold voltage (Vth) are two critical factors to achieve high performance pMOS-RADFET. In this paper, the Vth adjustment techniques for thick gate oxide by B+ implantation are simulated systematically by Silvaco TCAD, including implanting...
In this paper, we have analyzed for the first time that the body potential versus gate voltage characteristic curves for device having equal channel length but different body widths pass through a single common point called as ‘crossover point’, for triple gate (TriG) MOSFET. We have found that at this crossover point, there is no potential drop from body center to the surface in the Si body. However,...
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed.
This paper presents the effect SOI detector's bias voltage has on current-voltage characteristics of different types of transistors (core transistors, io transistors, body floating, sourcetie, body-tie, low/normal/high threshold voltage). Methods of minimizing this effect were presented. Also, the I–V characteristic of transistors utilizing shielding layer (BPW - buried P Well) were measured and presented...
Methods of a MOSFET threshold voltage extraction have been briefly described. A possibility of their application for characterization of a fully-depleted SOI MOSFETs has been discussed. A simple method for SOI MOSFET threshold voltage characterization has been proposed. The concept has been verified based on experimental data obtained for SOI MOSFETs manufactured in ITE.
Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical...
The embedded SiGe source/drain stressor helpful to promote the drive current involves etching out the source/drain silicon and replacing it with SiGe filler. This process uses the lattice mismatch between silicon and germanium atoms making the silicon channel compressive. This compressive stress enhances hole mobility, and the pMOSFET performance can be enhanced. In this study, the characteristics...
Strained Engineering including both global and local strains effectively enhances the mobility of carriers, in which global strains are generated by the mismatching of lattice constants at the junction of Si and Si0.775Ge0.225 and local strains are aroused by Source/Drain refilled with SiGe. In this paper, junction breakdown voltage, punch-through voltage, and the variation of threshold voltages are...
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