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This paper presents a topology which gives optimum performance in terms of operating frequency, speed of operation, power dissipation, Power Delay Product (PDP) and transistor count. The operation of the latch shown is controlled by the p-MOS and the n-MOS switches. Cascading two stages of the proposed latch incorporates a ‘divide by 2’ circuit whose simulation result is shown in Fig.2. The proposed...
The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage...
We present a new methodology for automatic selection and sizing of analog circuits demonstrated on the OTA circuit class. The methodology consists of two steps: a generic topology selection method supported by a “part-sizing” process and subsequent final sizing. The circuit topologies provided by a reuse library are classified in a topology tree. The appropriate topology is selected by traversing...
In this work, a methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented. To evaluate the usage of stacked devices, the characteristic curves of transistors implemented with a different amount of transistors in stack are obtained and compared to those of a single device. The effects of using stacked...
This paper presents a 300 MHz to 3 GHz Low-Noise Amplifier (LNA) with high HP3 and one of the smallest silicon area we could find. It is based on a single amplifier, where it is systematically optimized to achieve better results than more complex noise canceling topologies, thus, saving area and power consumption. A CMOS inverter with resistive feedback where transistors are self-biased in strong...
This work presents a six phase Switched Capacitor (SC) DC — DC converter for photovoltaic Energy Harvesting designed in a 130 nm CMOS process for commercial motes application and Internet of Things (IoT). It tracks the Maximum Power Point (MPP) of a commercial 3 cm × 3 cm 60 mW poly-crystalline photoelectric panel through switching frequency modulation aiming battery recharge. Open-circuit voltage...
Multilevel inverters allow to generate AC voltages with low total harmonic distortion (THD) but requires an increased number of power switches. One of the disadvantages of that is the increased probability of a fault in one of the power switches. Thus in order to improve the reliability of the converter a fast and robust fault detection scheme must be used. In this context this paper presents a new...
This paper represents a method to enhance the linearity of an integrator by implementing feedback compensation topology. The proposed design reduces signal swing while keeping advantages of both feed-forward as well as feedback topology without changing the signal transfer function. Linearity is related to the output of an integrator. Non-linearity resulted because of the integrator's output swing...
Multilevel inverter (MLI) is a proven technology used for control of electrical machines, grid integration of renewables and active power filtering. The recent trends show ingenious attempts to achieve maximum number of output voltage levels with minimum number of active device count and active device rating. This paper proposes a novel family of H Bridge MLI with transistor clamp to increase number...
This article presents the first experimental results of an integrating Radio-Frequency DAC (RF-DAC) we called the Riemann Pump. This DAC is part of a complete waveform generator architecture based on the quantization of the signal variations and the conversion of the as-obtained digital signal into the analog domain. This technique provides an improvement of the coding efficiency with respect to conventional...
Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS2. However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology...
This paper presents a power- and area-efficient three-stage amplifier suitable to drive high capacitive loads. The amplifier is compensated by a single Miller Capacitor and an additional feedforward stage. To improve the amplifier large signal transient response, the topology also includes an external feedforward path and a novel slew-rate enhancer section. Implemented in a 0.35-μm CMOS process, the...
In this paper, we propose voltage converter with high efficiency over wide input voltage. This converter is suitable for the solar panel for WSN applications where the only power source is a solar cell that outputs highly variable voltage. The aim is to achieve this by using multiple converter topologies in parallel. Use of such converter has a meaning in renewable resources that in the long term...
A new small-signal amplifying system with Sziklai pairs in triple transistor topology is proposed and qualitatively analyzed for the first time. Proposed amplifier design may be used at preamplifier stage of EEG, Radio/TV receivers and other audible frequency range communication systems. Combination of Q1-Q2 transistors in the proposed design constitutes PNP Sziklai pair whereas Q2-Q3 together acts...
Network on chip is a new trend in multi-core applications. Typically multiprocessor requires several Intellectual property (IP) cores based on the application needs. When the number of processing elements (PEs) increases in the multi-core device then a couple of problems encountered like traffic congestion, deadlock, interconnection problems, area, power latency and so on. There are several types...
Network on chip is a new trend in multicore applications. Typically multiprocessor requires several Intellectual property (IP) cores based on the application needs. When the number of processing elements (PEs) increases in the multi-core device then a couple of problems encountered like traffic congestion, deadlock, interconnection problems, area, power latency and so on. There are several types of...
The comparison element for a content-addressable memory is made on the STG DICE cell with transistors separated onto two groups and a logical element “Exclusive OR”. The comparison element contains two identical blocks that are spaced on the crystal by the distance of four micrometers. The simulation of the new 65-nm CMOS comparison element showed the resistance to impacts of single nuclear particles...
This paper presents a design of fully differential low-noise amplifier (LNA) used for 60 GHz low power wireless communication in 65 nm CMOS technology. The proposed LNA consists of an input stage employing capacitive cross-coupling technique and an gain stage using current-reuse techniques. The simulated amplifier achieves both input and output matching better than −15dB, a forward gain of 15 dB,...
A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed...
In this paper, a novel analog layout synthesis tool is presented. It is focused on two common analog building blocks: differential pairs and arrays of stacked devices. Starting from a circuit netlist and the names of the selected transistors, the tool verifies that these form a valid block and creates the corresponding layout. The user can define different layout parameters and the layout view can...
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