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This paper presents a topology which gives optimum performance in terms of operating frequency, speed of operation, power dissipation, Power Delay Product (PDP) and transistor count. The operation of the latch shown is controlled by the p-MOS and the n-MOS switches. Cascading two stages of the proposed latch incorporates a ‘divide by 2’ circuit whose simulation result is shown in Fig.2. The proposed...
In this paper the implementation of a low power high speed 3-bit Flash Type ADC is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the conventional comparator. The reported structure of the ADC occupies an active area of 0.012 mm2 and consumes 179 µWatt of Average Power while operating with an input frequency (fin...
In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 µW of average power while operating with...
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