This paper presents a topology which gives optimum performance in terms of operating frequency, speed of operation, power dissipation, Power Delay Product (PDP) and transistor count. The operation of the latch shown is controlled by the p-MOS and the n-MOS switches. Cascading two stages of the proposed latch incorporates a ‘divide by 2’ circuit whose simulation result is shown in Fig.2. The proposed circuit uses 12 MOSFETs which is lesser as compared to other topologies and consumes a power of 216 μW operating at a frequency of 0.5 GHz and a supply of 1.8 V. The proposed circuit has a very low average delay of 300 ps at 1.8 V supply, which makes it a better contender in high speed Frequency Synthesizers. The proposed circuit has a PDP of 6.48 ×10−14 J. The proposed circuit has been simulated in Cadence Virtuoso using 180 nm CMOS Technology and a supply of 1.8 V.