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This work investigates new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. We explore various options for implementing model redundancy, based on the use...
The high cost of testing certain analog, mixed-signal, and RF circuits has driven in the recent years the development of alternative low-cost tests to replace the most costly or even all standard specification tests. However, there is a lack of solutions for evaluating the parametric test error, that is, the test error for circuits with process variations, resulting from this replacement. For this...
Motion Estimation (ME) is the process of determining the motion vectors that describe the transformation from one 2D image to other, usually from adjacent frames in a video sequence. The process of ME is the critical part of any video coding system as the video quality will be affected if an error has occurred in the ME. In order to test Motion Estimation in a video coding system an Error Detection...
Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient...
This paper presents a fault model based test technique for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to test for structural defects such as gate-FOX breakdown, gate-stress due to thermal overload and drain leakage due to high voltage stress. We have developed highly accurate equivalent circuit models for HV-LDMOS which is represented as a hybrid model...
This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT). The proposed method controls the power supply voltage on an automatic test equipment (ATE) system in a feed-forward manner by supplying a compensation current into the power supply line based on the power supply voltage waveform difference between the...
In this paper a general modeling procedure for 1.2/50μs generator defined in IEC 61000-4-5 is presented. Subsequently, in PSpice this surge generator model is employed in order to simulate and observe surge tests for electrical vehicles, which have plugs to the public mains supply due to their charging systems. In the research several shielding set-ups of charging systems in electrical vehicles are...
A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected...
Simulation is an important method and tool in many fields of engineering. Compared to these, simulation plays only a minor role in the field of software processes and software engineering. Examining this discrepancy, four theses are formulated as suggestions for future directions of software process simulation: 1. Simulation requires efforts, but “not simulating” might cause considerable costs as...
This paper proposes a feasibility study of using Magnetic field property in detecting defects on printed circuit board (PCB) conductors. Simple microstrip transmission lines have been proposed and modeled as a non-defective line and defective lines in Computer Simulation Technology (CST) Microwave Studio in the purpose to observe the characteristic of magnetic field intensity (H) at 3 mm above the...
This paper presents a scalable electrical model for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to determine the I–V characteristics, which can be used in SPICE simulators. This scalable model is represented as a hybrid model by computing its transfer function to enable its wide use in testing high-voltage devices. The scalable model has been validated...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
The increasing demand for more sophisticated ICs with more functionality mostly was realized by downscaling and increasing the number of transistors. A technology that promises further increase of transistor density (in addition with heterogeneous integration, better performance and less power dissipation at a smaller footprint) is the three-dimensional stacked ICs (3D-SICs). Several stacking approaches...
Embedded systems in automotive engineering are getting more and more complex due to a higher rate of integration and shared usage of sensor signals. A common solution to testing these systems is deriving test cases from models, so called model-based testing. In practice, generated test suites are typically very huge and have to be reduced by methods of regression-test selection and prioritization...
Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations...
Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present...
The cost of integrated circuits increases with the complexity and integration density. This has led designers to consider testing from the design phase; that's what we call DFT (design for testability). In this paper, we propose a DFT solution, based on technique of IDDQ measuring current, by incorporating a Built-In Current sensor, whose function is to detect power consumption of different circuits...
Rewiring is a flexible and useful logic transformation technique through which a target wire can be removed by adding its alternative logics without changing the circuit functionality. In today's deep sub-micron era, circuit wires have become a dominating factor in most EDA processes and there are situations where removing a certain set of (perhaps extremely unwanted) wires is very useful. However,...
Test data collection for a failing integrated circuit (IC) can be very expensive and time consuming. Many companies now collect a fix amount of test data regardless of the failure characteristics. As a result, limited data collection could lead to inaccurate diagnosis, while an excessive amount increases the cost not only in terms of unnecessary test data collection but also increased cost for test...
In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments...
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