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Eukaryotic cells have complex regulatory systems that sense adversity (e.g. DNA damage, heat shock, external death-induction signals) and respond by invoking programmed cell-death or apoptosis. Cancer cells have evolved the ability to thwart such sensory information and associated regulation. As biologists begin to understand cells in circuit-like terms, we can also begin to derive and simulate druggable...
Adaptive time-stepping is crucially important for the efficiency of a circuit simulator. Existing time-stepping methods rely on information at prior time point(s) to select step sizes, which can be problematic when the circuit is undergoing a fast transition. In this work, we propose a new time-stepping method that solves the circuit equations together with the condition for local truncation error...
Today high-end cars have extremely complex E/E architectures - with 50–100 electronic control units (ECUs), connected by communication buses like CAN, FlexRay and Ethernet. They are used to run several (control) applications with many million lines of code. We propose a radically new architecture where all these applications are instead run on a mobile phone being carried by the driver. The car now...
For real-time tasks, cache behavior must be constrained via cache locking or predicted by WCET analysis. Since the former gives up energy efficiency for predictability, this paper proposes a novel code optimization that reduces the miss rate of unlocked instruction caches and, provenly, does not increase the WCET. We optimized the 37 programs from the Mälardalen WCET benchmark for 36 cache configurations...
Silicon physical unclonable functions (PUF) utilize fabrication variation to extract information that will be unique for each chip. However, fabrication variation has a very strong spatial correlation and thus the PUF information will not be statistically random, which causes security threats to silicon PUF. We propose to decouple the unwanted systematic variation from the desired random variation...
TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze...
With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel insitu timing error masking technique, namely InTimeFix,...
In this paper, we present a first general purpose GPU thermal management design that consists of both hardware architecture and OS scheduler changes. Our techniques schedule thread blocks from multiple computational kernels in spatial, temporal, and spatio-temporal ways depending on the thermal state of the system. We can reduce the computation slowdown by 60% on average relative to the state of the...
The computing market has been dominated during the last two decades by the well-known convergence of the high-performance computing market and the mobile market. In this paper we witness a new type of convergence between the mission-critical market (such as avionic or automotive) and the mainstream consumer electronics market. Such convergence is fuelled by the common needs of both markets for more...
Three dimensional (3D) integration attempts to address challenges and limitations of new technologies such as interconnect delay and power consumption. However, high power density and increased temperature in 3D architectures accelerate wearout failure mechanisms such as Negative Bias Temperature Instability (NBTI). In this paper we present VAWOM (Variation Aware WearOut Management), an approach that...
Statistical static timing analysis (SSTA) involves computation of maximum (max) and minimum (min) of Gaussian random variables. Typically, the max or min of a set of Gaussians is performed iteratively in a pair-wise fashion, wherein the result of each pair-wise max or min operation is approximated to a Gaussian by matching moments of the true result obtained using Clark's approach [1]. The approximation...
Adopting SSDs as caches for HDD arrays has gained popularity in datacenters because SSDs are superior in handling random reads that HDDs cannot efficiently deal with. Two types of flash memory cells are available for building SSD caches, single-level cells (SLC) and multi-level cells (MLC). MLC is more appealing than SLC because it can achieve higher cache capacity at the same cost. However, we see...
Three-dimensional Multicore Systems present unique opportunities for proximity driven data placement in the memory banks. Coupled with distributed memory controllers, a design trend seen in recent systems, we propose a Dynamic Memory Relocator for 3D Multicores (DMR3D) to dynamically migrate physical pages among different memory controllers. Our proposed technique avoids long interconnect delays,...
MLC Flash memory is getting more popular in computer systems ranging from sensor networks and embedded systems to large-scale server systems. However, MLC flash has many reliability concerns, including the potential for corruption due to supply voltage fluctuations. This paper characterizes MLC flash when the chip is under-powered (i.e., power fading and voltage droops). We demonstrate that underpowering...
A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement...
Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors...
The high cost of testing certain analog, mixed-signal, and RF circuits has driven in the recent years the development of alternative low-cost tests to replace the most costly or even all standard specification tests. However, there is a lack of solutions for evaluating the parametric test error, that is, the test error for circuits with process variations, resulting from this replacement. For this...
In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number of features. Next, we apply an unsupervised hierarchical clustering algorithm to divide wafers into...
Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon Nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement...
Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such equivalence checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate equivalence...
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