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Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high- gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL...
A comparative study has been made for open loop, set point controlled microcontroller based buck converter with Si and SiC diode. The simulation and hardware results indicate that both in charging mode as well as in discharging mode SiC has a better performance compared to that with Si diode. Hardware results show that settling time and peak overshoot reduced to a great extent when SiC (CSD04060)...
The most promising device in the Nano scale range are based on multiple gate structures such as double-gate (DG) MOSFETs. These devices could be used for high frequency applications due to the significant increase of the transition frequency fT for these devices. For low noise radiofrequency applications, high frequency noise models are required. In this paper, compact channel noise models valid in...
In this paper, we have explored the designing approach of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs, for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. This proposed CSDG MOSFET can be used as the RF switch for selecting the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the...
Dosimeters made of scintillating optical fibers have interesting properties and due to its small dimensions can found a field of application in brachytherapy. In this work we exploit the properties of such a dosimeter when irradiated with a clinical 192Ir radioactive source. Furthermore, we compare its response to the responses of an ionization chamber and a MOSFET dosimeter irradiated under the same...
We have investigated carrier transport properties in ultra-thin body (UTB) Ge-on-Insulator (GeOI) MOSFETs for the first time. Both n- and p-channel MOSFET operation fabricated on 9 nm GeOI has been demonstrated. In addition, a significant difference of Ge crystallinity in the front-channel from that in back-one is reported to explain the mobility degradation in UTB region.
In this paper, we propose a comprehensive model to express nMOSFET threshold voltage shift induced by the stress, ranging from high tensile one to high compressive one. Using this model, the quantum confinement effect is shown to play an important role to cause the threshold voltage shift as large as about 80mV induced by high-film-stress CESL.
This work presents the development of a novel bidirectional Solid State Disconnect (SSD) module based on Silicon Carbide (SiC) Junction Field Effect Transistors (JFET) capable of a fast disconnect action upon reaching a preset value of the current through the SSD. Due to the superior properties of SiC material and the low on-resistance of the normally-on SiC JFET, a very low insertion loss can be...
This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited...
We developed a procedure and software allowing us to predict and understand device performance by incorporating 2D-carrier profiles from high resolution scanning spreading resistance microscopy into a device simulator. We demonstrate the incorporation of the quantified SSRM 2D-profiles into a device simulator using data collected on p-MOSFETs. Based on these profiles the simulator now predicts the...
In this paper, we propose a fabrication process of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET). By employing TCAD tools, a systematic process simulation in realizing the SDP-MOSFET structure is done successfully. By using vertical and horizontal doping profiles, 120 nm gate length with 12 nm gate oxide of the device is observed respectively. The combination of a Silicon Germanium...
The significance of variation on tilt angle ion implantation for fabricating the Vertical MOSFET with ORI (Oblique Rotating Implantation) technique is investigated. For this purpose, the angle of the ion implantation for forming the source and drain region is varied from 0° to 80°. Various effects on physical structure of the device and its corresponding electrical properties have been observed. The...
A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0…0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220–240%...
The effect of substrate negative bias VB on the gate-induced drain leakage (GIDL) current is studied. It is found that the negative VB leads GIDL current curve shifts upwards. The shift of GIDL current ΔID/ID increases with increasing |VB|. The GIDL current at VG=−0.2V (in the low field region) increases with increasing |VB| more largely than that at VG=−1.2V (in the high field region). This is because...
The heavily doped n-type silicon nanowires (SiNWs) junctionless field effect transistors (JLFETs) are fabricated using the self-aligned process to control the position and direction of SiNWs. Aligned SiNWs are grown across the pre-patterned source and drain under the assistance of the externally applied electric field, which facilitate the subsequent device fabrication. The JLFET exhibits an electron...
An oxide/silicon core/shell nanowire (OSCSNW) MOSFET is proposed. Its fabrication process and performance are described in detail. The ION/IOFF ratio of the OSCSNW is improved by more than one order of magnitude compared with traditional nanowire (TNW) devices. Excellent scaling characteristics are also observed from the OSCSNW MOSFETs with minimal threshold voltage roll-off, drain induced barrier...
In addition to global stained epitaxial SiGe layer, silicon nitride as contact etching stop layer (CESL) is to be deposited on the whole device to enhance the straining effects. As found in this paper, 10μm/10μm (channel length/ width) PMOS devices at various temperatures with or without stain are referred. To focus on the SiGe alone, the 1.5nm silicon cap following epi-taxial SiGe is to be considered...
The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results...
Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation current is suffered. Through the deliberate pattern design, the fringe junction leakage for MOSFET device...
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