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An approach to simultaneously reduce the length of bond wires and trace parasitics within substrate-based, chip-on-board (COB), ball grid array (BGA) packages is presented. Three, two-layer, 8mm × 14mm COB BGA packages were modeled and analyzed using Ansoft Turbo Package Analyzer's (TPA) 3D boundary element method (BEM). The initial package design has long interconnecting bond wires from the die to...
Electrolessly plated Ni-P has been extensively studied due to its high coating uniformity, selectivity and low coating stress. However, the use of lead-free solders accelerates interfacial reaction because they have higher melting points and higher Sn content than the conventional Pb-Sn solders. In this work, we developed a ternary electroless Ni-Sn-P (6~7 wt.% of P and 15~17 wt.% of Sn) alloy to...
The advanced Quad Flat No-Lead (aQFN) package is an enhanced version of conventional QFN with multiple row terminals of featuring higher number of I/O ports. The aQFN thermal and electrical performance are superior due to smaller profile and shorter interconnects and the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the...
As gold price continues to move in an overall rising trend, conversion to Cu wire has been given great focus as the main effort for cost reduction. Cu is a good alternative due to 26% lower electrical resistivity than Au, hence much higher electrical conductivity. However, Cu free-air-ball and bonded ball hardness are 34% and 60% higher than that of Au, hence increases the stress on bond pad and chip...
To reduce the degradation of signal integrity in substrate-based, chip-on-board (COB), ball grid array (BGA) packages caused by excessive trace capacitance, a sensitivity study on package trace capacitance is presented. A test vehicle was designed and simulated for the sensitivity study using Ansoft high frequency structure simulator (HFSS). Nine potential package parameters that can affect trace...
This study describes board-level drop reliability of TFBGA subjected to JEDEC drop test condition which features an impact pulse profile with a peak acceleration of 1500G and a pulse duration of 0.5 ms. The solder ball is assumed as an elastoplastic model, and the other components are assumed to be linear elastic models. Both the global/local finite element method and the finite grid region method...
A global/local method along with an optimization algorithm, so called the modified sub-modeling approach of the optimal equivalent solder is introduced as a simple but effective approach to predict the deformation and the reliability in the package. The viewpoint of equivalent solder in this method is facilitated to obviously reduce the number of elements/nodes so as to enhance computing accuracy...
Transition to Pb-free has necessitated the requirement for study on the reliability of mixed assemblies. Mixed assemblies are bound to be used during the transition period and beyond the deadline as well. Processing and reliability issues with Pb-free manufacturing have forced the exemption of certain product categories from the legislations banning the use of lead. Hence, the use of mixed assemblies...
The demand for wireless communications is increasing through use of smart phones, 3G handsets wherein high speed and reliable data communication are crucial requirements. Multi-bands networks help to facilitate these at higher range of radio frequencies. In many wireless communications, power amplifiers (PA) are used to increase the amplitude of relatively weak signals. These PAs depend on matching...
The ever increasing power density in high performance microelectronic devices for large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. In this study, the effect of heatsinking compressive load on the...
The effects of material properties modeling on the solder failure analyses by numerical simulations are studied. The packaging structure of plastic ball grid array on printed circuit board was modeled. Two different types of molding compounds and two different types of substrates were employed and combined for the plastic ball grid array package modeling. The material properties were assumed as temperature...
In a flip chip package (FCBGA), the presence of stress arising from the thermal mismatch between different materials is inevitable. It is a challenge for the packaging community to manage these stresses via careful selection of materials and design to achieve optimal performance and reliability of the integrated circuit. Finite Element Analysis (FEA) modeling for thermomechanical study is a widely...
The objective of this paper is to present the key challenges in Silicon chip separation by mechanical dicing and changes needed in the saw street design to meet the additional demands in quality requirement put-forth by chip embedding packaging technology like the embedded Wafer Level Ball Grid array [eWLB]. When standard mechanical dicing process and saw street design meant for traditional packaging...
Although single die eWLB has been around for quite some time, processing of multi-die packages can pose many challenges. In multi-die eWLB package, two or more dies are placed side by side with a small gap, encapsulated by mold compound and interconnected with redistributed layers (RDL) and solder balls. The objective of this paper is to share the challenges in processing multi-die eWLB packages,...
In this work, a new empirical method is proposed to incorporate the initial substrate warpage into package stress simulation. As a first step, the bare substrate strip warpage characteristics were mapped. The out-of-plane displacements of the substrate strips were measured as a function of temperature using shadow moire technique. It was observed that the warpage values of the bare substrate vary...
This paper focuses on the 1.0 mil Cu wire development and its reliability performance mainly at component level of a BGA wire bond package which consists of 2 metal layer organic substrate more than 500 pin counts. This paper covers package reliability tests such as THB (Temperature and Humidity Biased test), unbiased HAST, TCB (temperature cycling B), high temperature storage tests on BGA laminate...
Copper (Cu) wire bonding is the most viable alternative interconnection technology to gold (Au) wire bonding when cost is considered. Recent developments in bonding technology and capability has resulted in copper wire bonding being targeted at high pin count and high performance applications such as ball grid array packages. Wire sweep performance is extremely important in high I/O products as slight...
As gold price continues to move in an overall rising trend, conversion to Cu wire has been given great focus as the main effort for cost reduction. Cu is a good alternative due to 26% lower electrical resistivity than Au, hence much higher electrical conductivity. However, Cu free-air-ball and bonded ball hardness are 34% and 60% higher than that of Au, hence increases the stress on bond pad and chip...
In PCBA manufacturing industry, corner adhesive was commonly used on BGA(Ball Grid Arrays) to resolve the solder joint crack induced by mechanical stress either during shock and vibration reliability test or during board manufacturing processes(ICT test fixture, router, handling and etc) especially for mobile motherboard. However, this solution imposed high manufacturing cost which required additional...
Most bumped packages (WL-CSPs, BGAs, etc) undergo the necessary 3D visual inspection in tray-scan machines or at the wafer level, or sometimes there is no 3D inspection, relying on process stability and correlation with 2D inspection alone. This means the device are further manipulated before they are placed into tape, and there is the risk of them being actually damaged. This risk is more important...
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