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The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
In this paper, three-stage operational transconductance amplifiers (OTAs) for use in switched-capacitor (SC) circuits using nanometer CMOS technologies are described. Two three-stage OTAs, one with nested-Miller compensation (NMC) as a basic compensation scheme and another with damping factor control frequency compensation (DFCFC) as an advanced compensation scheme are presented. The open-loop small-signal...
Multi-Threshold CMOS (MTCMOS) is one of the most used circuit techniques to reduce the leakage current in idle circuit. Ground bounce noise produced during transition mode (Sleep-to-Active) is an important challenge in MTCMOS. In this paper we have designed our multiplier with different MTCMOS techniques to reduce the ground bounce noise and leakage current. The dependence of ground bounce noise on...
Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in multi-threshold CMOS (MTCMOS) circuits. Different multi-phase sleep signal slew rate modulation techniques for mode transition noise mitigation are investigated in this paper. A triple-phase sleep signal slew rate modulation technique with a novel digital sleep signal...
This paper presents the design and characterization of SiGe RFICs for millimeter-wave radiometers. It is seen that SiGe technology results in high gain millimeter-wave amplifiers, high responsivity detectors and low overall 1/f noise, making it ideal for on-chip radiometers. Two example radiometer systems, one at W-band and one at D-band, are presented in detail.
This paper illustrates some design strategies for the design of mixed analog-digital integrated circuits in CMOS technology. In mixed-signal systems, crosstalk from switching logic gates can disturb the operation of analog circuitry. Therefore, it is necessary to take into account digital switching noise from early stages of design, by means of a suitable model. The analog designer should select the...
As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon,...
A single-pole double-throw novel switch device in 0.18 ??m SOI complementary metal-oxide semiconductor (CMOS) process is developed for 0.9 Ghz wireless GSM systems. The layout of the device is optimized keeping in mind the parameters of interest for the RF switch. A subcircuit model, with the standard surface potential (PSP) model as the intrinsic FET model along with the parasitic elements is built...
A 1.2 V 10 bit 83 MS/s pipeline ADC implemented in 130 nm CMOS Technology is described. Emphasis was placed on noise analysis and capacitance optimization. Experience of operational amplifier, comparator and switch design were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33 LSB respectively, while SNDR is 57.7 dB.
A method for realizing a phase shifter by employing switching transistors and transmission lines is proposed. The presented current switching phase shifter performs phase shifting by steering a current source to appropriate position on a transmission line. A 60-GHz phase shifter is implemented on a 65-nm CMOS technology using this method. The phase shifter can provide four quadrature phases for input...
This paper demonstrates a multi-band low noise amplifier (LNA) in 0.13 mum CMOS process, which is configurable with switching capacitor in 900 MHz, 1800 MHz, 2.4 GHz and 5.2 GHz bands. A dual-loop feedback technique is used to enhance the performance in noise figure, power gain and power consumption. The noise figures are 2.6 dB at 900 MHz, 2 dB at 1800 MHz, 2.1 dB at 2.4 GHz and 3.5 dB at 5.2 GHz;...
Based on the switched-capacitor discrete time sampling technique in 0.18 um CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16 bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The...
A digitally controlled variable gain amplifier (VGA) for low power, low-IF receivers is presented. The amplifier was designed and fabricated in IBM 7WL BiCMOS 180 nm technology. It shows a dynamic range of 45 dB with a maximum gain of 52 dB and a minimum gain of 7 dB. The gain variation is achieved by means of switched feedback resistors. These are controlled by a demultiplexer and 4 control bits...
A new output buffer with low switching noise and load adaptability is designed based on a TSMC 90 nm CMOS technology. The proposed buffer can reduce switching noise induced on supply lines and output ringing while achieving very fast output transitions. Moreover, the load adaptive method is simple and effective. Simulation results demonstrate that the proposed buffer achieves 4.1%-53.5% improvements...
A high-gain low-noise CMOS downconversion active folded mixer which can operate at 900 mV supply voltage is presented in this paper, and a LC circuit is introduced between the common source node of the switching pair to resonate out the parasitic capacitance in order to improve the performance. The mixer is designed in chartered 0.18-mum one-poly six-metal CMOS technology for 2.4 GHz ISM band applications...
In this paper, a 110 dB, 1.024 MHz fourth-order single-loop sigma-delta modulator has been presented with an over-sampling ratio of 128 and an overload factor of -6 dB for a bandwidth of 4 kHz. In particular, this Sigma-Delta modulator is well suited for atmospheric pressure sensor. The whole modulator consumes only 3-mW from a single 3.3 V supply in a 0.35-mum CMOS technology and chip size is 1.68...
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated...
A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple...
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