Based on the switched-capacitor discrete time sampling technique in 0.18 um CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16 bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The modulator is proved to be robustness, the high performance in stability, anti- mismatch, chip area, and the power consumption is only 2.6 mw when the power supply is 2.8 V.