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A method for realizing a phase shifter by employing switching transistors and transmission lines is proposed. The presented current switching phase shifter performs phase shifting by steering a current source to appropriate position on a transmission line. A 60-GHz phase shifter is implemented on a 65-nm CMOS technology using this method. The phase shifter can provide four quadrature phases for input...
This paper describes the system architecture and design procedure for an integrated 60-GHz direct-conversion transceiver with integrated digital control interface on a 130-nm CMOS process. This transceiver incorporates both a transmitter and receiver. The transmitter achieves a Psat of 6.5 dBm, an OPldB of 1.6 dBm. The receiver achieves a conversion gain of 8.1 dB with an IIP3 of -13.74 dBm.
This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter...
Modern systems require transceivers that deliver gigabit speeds are smaller in size with lower power consumption and cost than existing technology consequently high speed transceivers operating at 60 GHz and delivering multi-gigabit per second are receiving significant research interest. This paper describes a 60-GHz transmitter developed and tested on a 130-nm CMOS process.
A variable delay line (VDL) is designed on a 130-nm CMOS process. Post-layout simulation results show that the VDL has a phase tuning range of 100 degrees at 60 GHz. It exhibits a wideband matching to 50-Ohm terminations from 20 GHz up to exceeding 80 GHz. The group delay variation is less than 4 ps within a bandwidth of 10 GHz. At its maximum phase shift, the VDL introduces a loss of 6 dB. The design...
The design of two critical building blocks for the realization of an all-integrated transceiver, the power amplifier (PA) and the transmit/receive switch (T/R switch), using a 130-nm CMOS process will be presented. The PA operating from a 2.5-V supply exhibits an output referred P1dB of 9.0 dB, a PSAT of+13.1 dBm, with peak power gain of 14.9 dB, a 3-dB bandwidth of 6.7 GHz, and 2.8 % power added...
A single-pole double-throw (SPDT) transmit/receive switch (T/R switch) operating in the 57-66 GHz band is implemented on a 130-nm CMOS process. The switch exhibits an insertion loss from 4.5 dB to 5.8 dB, an isolation from 24.1 dB to 26 dB, a return loss at antenna port from -9.2 dB to -10.5 dB, and a return loss at Tx/Rx port below -15 dB for the frequency band. With a control voltage of 1.2 V the...
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