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In this study, the influence of a temperature annealing process on the crystallographic orientation and sheet resistance of Pt/Ti films is investigated. Varying parameters are the annealing temperatures ranging between 450°C and 700°C and the atmosphere of the annealing process, which consists of either air, forming gas and argon gas. The thickness of the Pt/Ti film and the time of the annealing process...
This work presents the first transimpedance amplifier with a common gate input stage and a voltage-controlled resistor fabricated using organic thin-film transistors on a flexible plastic substrate. The presented circuit is tested in a photodetector application and shows a very low power consumption of 1.6 μW. The voltage-controlled resistor is the first resistor based on organic thin-film transistors...
Quasi-monocrystalline germanium (QMC Ge) is investigated for potential applications in high-efficiency, low-cost multi-junction solar cell design. The morphology and electrical resistivity of QMC Ge is characterized and computer simulations of MJSCs on Si substrates using QMC Ge interface layer are developed.
The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin...
This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution...
This paper demonstrates fundamental evaluation results of a C-band rectifier using Si substrate for HySIC application. Usage of the Si substrate is attractive for future integration with other mixed signal circuit. Because of large loss tangent of the Si substrate, applicability as a circuit substrate to the C-band rectifier is discussed. Two types of the rectifier, conventional printed circuit board...
The possibility of the surface-activated bonding (SAB) technologies for fabricating III-V-on-Si hybrid tandem solar cells is discussed. Although the electrical conduction across the bonding interfaces is influenced by the interface states introduced during the surface-activation process, their impacts are likely to be lowered by combining more heavily-doped bonding layers and the annealing process...
This paper presents the design and optimization of a square spiral using layout optimization technique. The ohmic losses are reduced by varying the width of the spiral segments with the outermost segment having a wider width and the innermost segment having a narrower width. The spiral shows a reduction in series resistance, and a significant quality factor improvement of about 11%.
VOx microbolometer, which is coupled with thin-film spiral antenna, was fabricated on a Si3N4/SiO2 membrane by metal-organic decomposition (MOD). The DC sensitivity of the device was 3120 W−1 and this value is about two orders of magnitude higher than that of the Bi bolometer fabricated on a dielectric substrate. The responsivity of the device was 370 V/W at 190 GHz for Ib = 50 μA.
This paper presents a continuation of an investigation into the behavior of lead magnesium niobate-lead titanate, Pb(Mg0.33Nb0.67)0.65Ti0.35O3) (PMNT) thin film at high frequency through electromagnetic (EM) simulation. The purpose of this paper is to improve the electrical characteristics. The electrical characteristics were analyzed on CPW built on PMNT thin films. In this study, we focus on the...
A high efficient CMOS class-E power amplifier (PA) by using Quad Flat No-leads (QFN) package combined with Through Silicon Via (TSV) grounding is presented. TSV has much smaller parasitic inductance and resistance than wire-bonds. TSV technology can improve PA efficiency, reduce die size samples and retain low cost in QFN package. The TSV samples are made and measured by using double-side probing...
Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are mitigated in all-Cu interconnects. In this...
We propose a two-pronged approach to reducing the impact of thermal cross-talk between components of disparate thermal operating points within a heterogeneously integrated electronic package. First, a low thermal conductivity interposer enhanced with an array of conductive thermal vias is employed to provide a high degree of lateral thermal isolation while providing adequate conduction in the vertical...
In system level electromigration test of 2.5D IC, Joule heating enhanced electromigration failure has been found to occur in redistribution layer in the interposer. In our test samples, there are two redistribution layers (RDL), each between every two levels of solder joints, so there are three levels of solder joints. First, the microbumps connect a Si chip on top and an interposer chip in the middle...
The relentless shrinking of microelectronic devices makes thermal management an increasingly important topic. To this end, we have developed a computational approach, which allows the prediction of heat flux in nanostructures based on atomistic simulations. As prototypical system, we present results for a silicon — silicon dioxide nanostructure, with (a) abrupt interfaces, and (b) interfaces after...
With the growing demand for mechanically flexible electrical systems and the increasing level of integration of electrical assemblies, hybrid build-ups combining polymer substrates and ultra-thin flexible silicon chips (system-in-foil) are getting more and more important. These systems need thin chips which maintain their functionality even in bent condition as well as reliable handling and assembly...
With the semiconductor development, more and more different devices need be integrated to achieve faster and more functionalities. Micro-bump is an important connection from chip to chip, chip to wafer and chip to substrate. We evaluated micro-bump barrier layer Ti thicknesses (400Å, 1KÅ and 2KÅ) effect on shear strength and bump chain resistance in this study.
In this paper, we demonstrate an ACF-packaged ultrathin Si-based flexible NAND flash memory by adopting a simple method, without using a conventional transfer process. By gently etching the bottom sacrificial silicon of the SOI wafer, flip-chip bonded devices were sufficiently thinned down (roughly to 1 μm) to fabricate highly flexible, fully packaged Si-based NAND flash memory, without any cracks...
This paper proposes the possible physics-based model for the conductive filament (CF) at the low-resistance state (LRS) of thin SiO2 films that were formed by sputtering technique. The closed and analytical current models proposed here are examined by experimental results.
We present a newly-developed three-dimensional (3D) physical simulator suitable for the study of resistive random-access memory (RRAM) devices. We explore the switching behavior of Si-rich silica (SiOx) RRAM structures, whose operation has been successfully demonstrated experimentally at ambient conditions [1]. The simulator couples self-consistently a simulation of oxygen ion and electron transport...
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