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FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant...
We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.
In this paper we demonstrate an efficient Si3H8, (SiH3CH3, and PH3) based deposition process that can be combined with a Cl2 based selective chemical vapor etch process. Various options for Cl2 based SiCP/SiP processes have been discussed and demonstrated [1-4]. The most efficient processes are isothermal and isobaric, since temperature or pressure changes add processing time, introduce complexity...
The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO2/TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO...
Steep channel impurity-profiles formed by Si:C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si:C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.
In this paper we compare two innovative approaches to the integration of Ge-channel on Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge-condensation process, and the second one relies on the epitaxy of a pure ultra-thin 2.3 nm-thick Ge layer performed directly on Si. With the second approach, we demonstrate for the first time highly-performant Localized GeOI...
This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint Wdesign. We compare the fabrication...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A new process is presented for building stacked CMOS transistors with high device quality. Device deterioration on bulk devices was minimized by reduced temperature processing for the SOI device, and the use of epitaxial lateral overgrowth to produce the silicon film for top devices improved film quality. The application of chemo-mechanical polishing allowed realization of 0.7??m silicon films with...
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