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The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM TEG array. It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to VDD terminal. The mechanism of the phenomena is also analyzed by measuring VTH of all transistors before and after stress and it is newly found that |VTH| of...
Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs are analyzed by decomposing into current variability components and compared with conventional bulk MOSFETs. It is found that drain current variability in SOTB MOSFETs is largely suppressed thanks to not only reduced VTH variability but also reduced current-onset voltage (COV) variability due to intrinsic channel.
We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable...
In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory...
Power consumption and thermal management are significant challenges in electronics, from mobile devices to data centers. A fundamental examination of such aspects could lead to orders of magnitude improvements in energy efficiency. We present recent highlights from our work examining dissipation in nanoscale devices, at contacts, interfaces, and in novel materials. Advances include the use of high-thermal...
Gate-all-around poly-silicon nanowire (GAA poly-Si NW) SONOS devices embedded with silicon nanocrystals (Si-NCs) were fabricated and characterized. As Si-NCs are incorporated, the transfer characteristics show a large clockwise Id-Vg hysteresis and a small kink under reverse sweep. Si dangling bonds located at SiNC/nitride interfaces are suspected to be responsible for the observations.
Random Telegraph Noise (RTN) has been shown to surpass random dopant fluctuations as a cause for decananometer device variability, through the measurement of a large number of ultra-scaled devices [1]. The most worrisome aspect of RTN is the tail of the amplitude distribution - the limiting cases that are rare but nevertheless wreak havoc on circuit yield and reliability. Since one cannot realistically...
A recently developed series resistance (RSD) extraction procedure from a single nanoscale device is shown to be highly robust. Despite these virtues, the technique unexpectedly results in a channel length-dependent RSD which is observed across a wide range of channel lengths and across many different technologies (SiO2, SiON, and high-k) (see Figs. 1a–f). This observation obviously raises some concerning...
We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.
We propose the feasibility of bidirectional selection device characteristics in ultrathin (<3nm) TiO2 layer. We utilized the localized conducting path as virtual electrode to investigate device property at extremely scaled area. By using electrical method such as “forming” and “reset” processes in oxide, virtual electrode/sub-3nm-thick TiO2/virtual electrode structure was achieved. The measured...
Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.
The 2012 IEEE Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It is the seventeenth workshop in the annual series, which showcases original work on nanometer8scale devices and technologies that utilize silicon or which are based on silicon substrates. The program this year includes 8 invited talks, 27 oral presentations,...
In this study, we for the first time assess the characteristics and sensitivity of p-type junctionless (JL) gate-all around (GAA) nanowire transistor using 3D quantum transport device simulation for CMOS technology implementation. Since the doping concentration of p-type junctionless nanowire transistor does not as high as in n-type device due solid solubility of boron in silicon, it can be made by...
Copyright (c) 2012 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of US copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided that the per8copy fee...
This paper presents experimental results of the counter dipole formation in SiO2/high-k (Al2O3 and Y2O3)/SiO2/Si gate stacks for the first time. The results definitely support the high-k/SiO2 interface dipole layer formation in metal/high-k gate CMOS.
Graphene nanoribbons with armchair-edged configurations (A-GNRs) are expected to be a channel material for higher-speed operation of FETs, since they have an almost linear dispersion relation despite the opening of a finite band gap and hence high carrier velocity up to 5 × 107 cm/s is predicted [1,2]. However, in actually fabricated GNRs with the current technologies, the ribbon width and edge configuration...
III–V compound semiconductors are expected as a post-Si channel material, because they have higher electron mobility and lower effective mass than Si. Actually, the high performance of InGaAs MOSFETs with high-k gate dielectrics has been demonstrated [1,2]. On the other hand, due to a quasi-ballistic behavior of electron transport, III–V channel MOSFETs may be more vulnerable by quantum mechanical...
In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when...
Over the past decade we have developed a radical new strategy for the fabrication of atomic-scale devices in silicon [1]. Using this process we have demonstrated few electron, single crystal quantum dots [2], conducting nanoscale wires with widths down to ∼1.5nm [3] and most recently a single atom transistor [4]. We will present atomic-scale images and electronic characteristics of these atomically...
Using low temperature measurements we have been able to identify the influence of only about five donors in the channel the channel of an ultra-scaled MOSFET as the source of an anomalously low room temperature threshold voltage and large sub-threshold slope. Futher we observe the influence of these dopants on the low temperature threshold voltage shift as a function of applied back gate voltage....
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