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In the past several decades on-chip dimensions have scaled over 2000X, while dimensions on printed circuit board have scaled 4-5X. This modest scaling of packaging dimensions has severely limited system scaling. To address this, we have proposed a disruptive package-free integration scheme. We replace the traditional organic printed circuit board (PCB) with silicon interconnect fabric (SiIF) and replace...
A fabrication process is demonstrated to form curved image sensors based on CMOS image sensor technology. A stretchable polymer backplane is fabricated monolithically on the backside of the wafer before a DRIE etch is performed to segment the wafer and make the circuit stretchable.
We demonstrate a fully integrated photonic network-on-chip (NoC) circuit comprising of more than 400 components realized in heterogeneous silicon photonic process offering 2.56 Tbps transmission capacity.
In the big data era, a new computing system, called Cognitive Computing, that can handle unstructured data, learn and extract the insights is required. A neuromorphic device is a key component for this, and several architectures are reported. Compared to the neuromorphic device with SRAM-based spiking neural network, a cross-bar structure device realizes on-chip leaning, but requires high-density...
In the big data era, a new computing system, called Cognitive Computing, that can handle unstructured data, learn and extract the insights is required. A neuromorphic device is a key component for this, and several architectures are reported. Compared to the neuromorphic device with SRAM-based spiking neural network, a cross-bar structure device realizes on-chip leaning, but requires high-density...
The growing complexity of todays technical systems demands for improved simulation techniques. One important aspect is the way how hierarchy of interconnected dynamical systems is handled. Focusing on this, some existing approaches are reviewed and a modified component connection modeling (CCM) framework is introduced. Furthermore, several conceptual considerations of CoSimMA, a modular simulator...
In this paper, silicon/glass/organic interposers for 2.5D/3D interconnects are investigated for signal integrity analysis. As total system bandwidth increases, memory industry has been developed to satisfy its requirements. Therefore, High Bandwidth Memory (HBM) is introduced to the market. HBM enables TeraByte/s bandwidth with extremely fine pitch, short interconnects using Through Silicon Via (TSV)...
In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small...
An overview of three-dimensional integrated circuits (3D ICs) is presented in this paper. The key potential applications of 3D ICs that have the most impact in terms of performance, power and area are highlighted, followed by a brief overview of the different technology approaches to implement 3D ICs. Further, the key challenges to 3D integration are discussed here.
Using newly developed silicon micromachining technology that enables low-loss and highly integrated packaging solutions, we are developing vertically stacked transmitters and receivers at terahertz frequencies that can be used for communication and other terahertz systems. Although there are multiple ways to address the problem of interconnect and packaging solutions at these frequencies, such as...
Quantum engineering is an emerging discipline, which involves studies of materials, devices, circuits, and architectures that are necessary to develop quantum-based systems. Recently, quantum computing has received significant attention, and large investments have been made in this field. Is this interest pure hype, or should we revise our views on computing? This Panel will address this question...
The emergence of three dimensional (3D) interconnects has reduced wire floor planning problems, increased device density, reduced RC wire delay, and minimized the energy dissipated by the long planar wires. Vertical 3D interconnect refers to a conductive filled through silicon vias (TSVs), which electrically connects front and back side of a silicon layer. Few electrical models and characterizations...
This paper compares the transient characteristics of aluminum (Al) and copper (Cu) microstrip line structures. Interconnects are represented using distributed resistance inductance capacitance (RLC) transmission line (TL) model. The equivalent RLC-ladder networks for Al and Cu interconnects are first implemented using VHDL-AMS, and their time-domain simulation responses are compared. For the verification...
Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias. This paper describes some of the major challenges related to testing of 2.5D ICs and presents some solutions to these problems. We first describe a test architecture using e-fuses for pre-bond interposer testing. We next present an efficient built-in self-test (BIST) technique that...
In this work, a 3-D IC architecture is proposed that composes an odd tier-number to provide enough flexibility to a circuit block at a specific tier to connect blocks at all other tiers. For a three-tier structure, it provides flexibility to a circuit block at the bottom or top layer in order to simultaneously connect blocks assigned to other layers. Such architecture would result in lower thermal...
As the density of 3D interconnects is increasing exponentially when scaling to lower levels of the interconnect wiring, in most cases 3D interconnect pitches of 5 μm and below will be required. Dielectric wafer to wafer bonding with via last integration can offer these interconnect densities. Wafer-to-wafer alignment and its impact on via last alignment are discussed. By taking into account current...
Most microsystem interconnections are formed using wire bonds or bump bonds. Industries and national laboratories have been jointly pursuing a partially 3D interconnect technology, which has the potential to increase the amount of circuitry per pixel by a factor of 2–3 This development effort has taken considerable time and resources, while producing very modest results due to the intrinsically difficult...
In this paper we propose an innovative three-layered 3-D IC structure with unequal die areas. It provides flexibility to a circuit block at the bottom or top layer to simultaneously connect to blocks assigned to other layers. Previously with regular structure, only a block at the middle layer used to be provided with this advantage. Based on the planned structure, a partitioning and layer assignment...
3D interposers are one of just a few ways of making electronic systems faster and more powerful, but their design can be complex. This paper presents a optimization flow to assist the design of silicon interposers with the highest bandwidth density possible. Using the methodology described in this paper, simulations have shown that chip-to-chip links on a silicon interposer can achieve bandwidth densities...
As the electronic devices miniaturization roadmap trend is pursuing, 3D technologies have also emerged and appeared as one serious option for the next generation of semiconductors industry. The purpose of this paper is to introduce the complete development of fine pitch microbumps and micropillars for chip to wafer interconnections on 300 mm wafers using industrial tools and with already existing...
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