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Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks,...
We demonstrate wavelength locking of a silicon ring modulator across 480pm laser wavelength drift using a drop-port OMA monitoring CMOS circuit and a dithering-based feedback loop at a settling speed of up to 380pm/s.
2.5D silicon interposer, for a cost effective optoelectronic package, is proposed and fabricated on a wafer level. Using this packaging approach, the fully assembled 120 Gb/s transmitter is scaled down to 6mm × 7mm.
We have investigated CMOS photonics based on heterogeneous integration of SiGe/Ge and III–V semiconductors on Si, which gives us opportunities to enhance functionalities of Si photonics through their superior material properties for electronic-photonics integrated circuits.
CMOS and tunneling-FETs (TFETs) utilizing high mobility III–V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport and tunneling properties. We addressed key issues to enhance the performance of III–V MOSFETs and TFETs. For the technologies enhancing the...
In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III–V compound semiconductors have emerged as a credible alternative. To get to this point, fundamental technical problems had to be solved though there are still many challenges that need to be addressed before the first non-Si CMOS technology becomes a reality. Among...
III–V integration on Si is one of the most attractive options to extend future CMOS circuits. However, direct material integration by epitaxial growth is challenging mainly due to the large lattice mismatch. Here we present a novel technique that enables InAs and GaSb nanowires to be grown on Si substrates in the same MOVPE run. By reducing the Au seed size, the nucleation of GaSb can be suppressed...
The cutoff frequencies and maximum frequencies of operation of short channel transistors have reached the terahertz (THz) range. In such devices, the ballistic electron transport, which was first proposed nearly 40 years ago, affects all the device characteristics - from the linear region (dominated by the so-called “ballistic mobility”) to a high field region affected by the ballistic injection....
Integration of GaN high voltage transistors into Silicon CMOS could combine superior electrical parameters of GaN HEMTs and the huge logic functionality of Silicon CMOS. Several issues of a monolithic integration of GaN devices into CMOS like material mismatch and thermal budgets can be overcome by heterogeneous integration by micro Transfer Printing. Results of first printing experiments with small...
In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of "Unwanted...
Carbon nanotube field effect transistor (CNFET) is one of the most promising emerging technologies, which can potentially outperform the conventional silicon technology with higher speed and lower power. However, most emerging technologies, including CNFETs, often face the challenge of lower device yield due to imperfect material processing. This paper studies the impact of imperfection of CNT substrates...
Discrete gallium nitride high electron mobility transistors (HEMTs) are fabricated on oriented silicon, then undercut and assembled onto non-native silicon CMOS wafers by elastomer stamp micro-transfer-printing. The thin, less than 5 µm thick, gallium nitride transistors were then electrically interconnected using conventional thin-film metallization processes. Electrical measurements reveal that...
We review the challenges and suggest future directions of carbon nanostructure CMOS integration for lab-on-a-chip systems. Power and area requirements of standard benchtop sensor instrumentation limits their use in portable applications. We have been developing carbon based nanostructures and low power analog readouts to enable sensitive and highly efficient sensor measurement in a single measurement...
We propose a two-pronged approach to reducing the impact of thermal cross-talk between components of disparate thermal operating points within a heterogeneously integrated electronic package. First, a low thermal conductivity interposer enhanced with an array of conductive thermal vias is employed to provide a high degree of lateral thermal isolation while providing adequate conduction in the vertical...
Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage...
Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
Ten years ago, at 90 nanometers, EDA was challenged and deemed inadequate in dealing with increasing complexity, power consumption, and sub-wavelength lithography, thus harming the progress of mobile phones. Today, at 10 nanometers, integration capacity has increased by two orders of magnitude, power consumption has been successfully “tamed”, and 193 nanometer immersion lithography is still relied...
Throughout the last decade, the microprocessor industry has been struggling to preserve the benefits of Moore's Law scaling. The persistent scaling of CMOS technology no longer yields exponential performance gains due in part to the growth of dark silicon. With each subsequent technology node generation, power constraints resulting from factors such as sub-threshold leakage currents are projected...
Pulse-based ultra-wideband (UWB) transmission has been identified as one of the emerging opportunities for high data rate communications in the microwave and millimeter-wave frequency ranges. In this frame, monocycle pulse emerged as one of the most interesting pulse formats candidate in support of next-generation (5G) UWB communications. However, the silicon implementation of narrow monocycle pulses...
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