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A capacitor voltage balancing method for a three phase modular multilevel DC-DC converter (MMDC) is proposed in the paper. The MMDC is derived from a three phase DAB and a modular multilevel converter (MMC) and inherits desirable features of both topologies. To guarantee stable operation of the MMDC, submodule (SM) capacitor voltages are required to be balanced. The proposed balancing method is to...
Reliability of power semiconductor switches is important when considering their vital role in power converters for aerospace, railways, hybrid electric vehicles, and power system applications. Due to technology advancements in material sciences, power MOSFETs manufactured with wide band gap materials such as silicon carbide (SiC), gallium nitride (GaN) have been proposed as an alternative to existing...
This paper presents short-circuit test results on commercial, multi-chip 1200 V SiC MOSFET half-bridge modules up to 860 V dc, suitable for three-phase 480 V grid-interfaced applications. The peak short-circuit current is measured to be over 5 kA, with around 3 μs withstand for the given voltage and commutation loop inductance. During the post-failure investigation, it is observed that only a few...
Charge trapping properties of Al-ZrO2/Al2O3/ZrO2-SiO2-Si structures were investigated in attempt to elucidate the instability in their C-V hysteresis. The hysteresis in these structures is mainly due to subsequent trapping of electrons and holes injected from the Si substrate. However the competitive process of electron injection from the gate accompanied by the high leakage introduces instability...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
Cathode related current collapse effect in GaN on Si SBDs (Schottky Barrier Diode) is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-VDP (Van Der Pauw) are associated with temperature dependent dynamic Ron transients analysis showing that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation...
Channel thickness Tch dependence of electron mobility μκρρ in thin In0.53Ga0.47As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed ID-measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion...
High mobility oxide TFT has been proposed for OLED panel integrated with scan driver and compensation circuit in pixel. The oxide TFTs on PI substrate has been developed to have 50 cm2/V-sec of mobility and less than 0.5V of range in threshold voltage. PBTS instability has been optimized to show ΔVth under 1V after extrapolation up to 3 years, comparable to PBTS characteristics of LTPS TFT. 5.5-inch...
The effects of ALD deposition temperature for the HfO2 gate insulator (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature was varied to 200, 225, and 250 °C. The HfO2 thin film prepared at 250 °C showed lowest leakage current density of 9.6×10−9 A/cm2 and highest dielectric constant of 23. The IGZO TF Ts using the HfO2 GI...
The amorphous Indium-Tin-Zinc Oxide (a-ITZO) was fabricated by using direct-current (DC) sputtering method. Electrical and chemical properties of a-ITZO thin film transistors (TFTs) fabricated on the polyimide (PI) substrate were investigated. The a-ITZO TFTs on the PI substrate exhibited the saturation field effect mobility of 8.93 cm2/Vs, subthreshold swing of 0.38 V/decade and high on/off current...
The Vth shift (ΔVth) of a-IGZO devices with gate dielectrics of Al2O3 and TEOS oxide after at a gate bias of + 20 V for 3600 s are +3.66V and −2.18V, respectively. Moreover, the Vth shift of two stacked dielectrics Al2O3 /TEOS oxide by using the equivalent capacitance with 100-nm-thick TEOS oxide. Two stacked dielectrics with a 10-nm-thick Al2O3 and a 96-nm-thick TEOS oxide, ΔVth decreases to −0.42V...
RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality...
In this paper, we present the experimental I-V and C-V characterization of vertical trench DMOS with different gate electrode recess depths. NBTI/PBTI test, via static bias stress test method was also performed in order to identify possible contaminations of the channel region. Effects of increasing this recess depth on the main electrical and capacitance performances are accurately measured. We concluded...
Negative Bias Temperature Instability (NBTI) is a prominent physical failure mechanism which severely degrades the performance of PMOS transistors whenever the voltage at the gate is negatively biased. It leads to catastrophic timing violations in critical circuits and a severe shortening of the overall operational lifetime of the entire system. To alleviate such damaging effects due to NBTI, we present...
The continuous scaling of device dimension and the introduction of FinFET technology has led to new reliability concerns, such as Bias Temperature Instability (BTI), Stress-Induced Leakage Current (SILC), Self-Heat Effect (SHE) and Time Dependent Junction degradation (TDJD). These reliability issues become process and design bottle neck for the advanced technology development because of their stringent...
In this paper, the gated imaging technique of dynamic photon emission is realized and introduced as a powerful localization tool by using a low-cost near-infrared InGaAs image intensifier (I.I). At first, the setup and the method for gated imaging of photon emission microscope (GI-PEM) are presented. As one of global localization tools, it shows an unique and economical debugging and pinpointing capabilities...
This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots,...
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