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In this paper, we introduce Jenga, a new scheme for protecting 3D DRAM, specifically high bandwidth memory (HBM), from failures in bits, rows, banks, channels, dies, and TSVs. By providing redundancy at the granularity of a cache block–rather than across blocks, as in the current state of the art–Jenga achieves greater error-free performance and lower error recovery latency....
Integrated circuits (ICs) undergo dimensional reduction and the functional unit of density dramatically increases, the reliability issue becomes more critical, especially with respect to three-dimensional (3D) silicon integration technology. Through-Silicon Vias (TSVs) technology is one of the most prominent feature used for interconnecting between chips. Since TSVs contain interfaces of heterogeneous...
A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via (TSV)-based vertical links (VLs) as the communication pillars between the planar dies. However, the TSVs in a 3D NoC may fail due to both workload-induced stress and crosstalk capacitance. This failure negatively affects the overall...
This paper reports on 3-D Via crosstalk characterization in three-dimensional integrated circuits. Several physical and environmental configurations are investigated using a 3D electromagnetic field solver. In particular, this work shows a detailed study on the influence of signal-ground 3D-Via locations, distances and their structural configurations on crosstalk. Simulation results are presented...
This paper presents on-chip self-testing circuits to detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ring-based oscillator test structure is proposed and simulated based on a...
In 3D integrated microelectronics, the failure analysis of through silicon vias (TSVs) represents a highly demanding task. In this study, defects in tungsten coated TSVs were analysed using scanning acoustic microscopy (SAM). Here, the focus lay on the realization of an automatized failure detection method towards rapid learning. We showed that by using a transducer of 100MHz center frequency, established...
Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal stresses under temperature loading, often leading to mechanical failure. A failure stress mathematical model is established and the algorithm of mathematical...
This paper presents the modular extension of a BiCMOS technology. Three different modules, namely RF-MEMS switch, through-silicon-via (TSV) and microfluidics, are added to IHP's BiCMOS technologies. The first extension module of RF-MEMS switch adds a high-performance mechanical switch, providing unique features such as low-loss switching at mm-wave frequencies. The TSV module, adds deep vias through...
The main reason to invest in 3D circuits adoption is the possibility of decrease the wire length, replacing horizontal wires by shorter vertical through-silicon-vias (called of TSVs). As a consequence, a better performance is expected and other optimizations also can be obtained in comparison with planar technology. In relation to 3D circuits, the networks-on-chip (NoCs) receiving special attention...
Thermal issue is a leading design constraint for three-dimensional integrated circuits (3D-ICs) and through silicon vias (TSVs) are used to reduce the temperature of 3D-ICs effectively. In this paper, the finite difference method-based heat conduction equations is proposed for the thermal analysis of the TSV structures in 3D-ICs and generalized minimum residual method (GMRES) with symmetric successive...
A non-contact TSV fault detection method is proposed using capacitive coupled probing. The proposed method detects TSV faults by eye-pattern diagrams of extracted EM-modeled transfer characteristics. The TSV and a capacitive coupling is modeled using full wave analysis. Because the measurement is conducted by moving one top probe without contact alignment, it can achieve the fast detection. Moreover,...
A silicon membrane acting as an interface layer between live cells and the sensing electronics enabling low-cost, high-throughput bio-sensing is proposed; the interface is capable of supporting high pixel density allowing accurate image mapping. Cell attachment and growth was carried out on five different silicon based surfaces and compared to the standard Tissue Culture Polystyrene (TCPS) surface...
3D technologies offer significant potential to improve total performance and performance per unit of power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create sophisticated logic on logic solutions that promise further increases in performance/power beyond those attributable to memory interfaces alone. These include heterogeneous integration...
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast...
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast...
Current innovations in electronics combine performance, size and cost criteria. Nevertheless, in the all-digital era, the 2D technology and the fabrication of CMOS Integrated Circuit are approaching their ultimate limits. As a result, the use of 3D technology in the fabrication of different Integrated Circuits becomes very appealing. Among the aspects of the 3D Integration we find the Through Silicon...
Thermal crosstalk within a heterogeneous 3D IC results in higher temperatures for low-power dice; this is particularly true in memory-logic, photonic-logic, and MEMS-logic stacks. The elevated temperatures may consequently impact the performance of the low-power devices. This paper describes a thermal solution for both heat removal as well as thermal isolation within a 3D chip stack. Based on the...
Three-dimensional (3D) integration has been considered as the most promising method to overcome the interconnection bottleneck with through-silicon vias(TSVs) served as vertical signal channels. Three-dimensional integrated circuits (3D IC) meet the demands of high throughput, high scalability and low power consumption for future generation integrated circuits. Crosstalk is the dominant problem in...
The superfilling of through silicon vias (TSVs) is a technical challenge for the fabrication of modern 3D Electronic packaging. In order to achieve void-free-filling for TSVs with different aspect ratios, various organic additives need to be added into the plating bath. Since TSV filling is a complex electrochemical and physical process, it is difficult and very time-consuming to get an optimal additive...
Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay...
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