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Despite the numerous benefits offered by 2.5D/3D integration, testing remains a major obstacle that hinders its widespread adoption. Concerns related to test cost, yield and reliability continue to derail the commercial exploitation of 2.5D/3D ICs. Test techniques and design-for-testability (DfT) solutions are now being explored in the research community, with considerable focus on wafer probing,...
With ever increasing complexities and a component-based design style there is a growing number of unknowns (e.g., at the interface of components) and their handling becomes more and more important in electronic design automation (EDA) and production processes. Methods and tools are required that in principle allow a modeling of unknowns balancing between exactness of representation and efficiency...
The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded...
The computing demands of future abundant-data applications far exceed the capabilities of today's electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented...
Non-volatile memories based on electron spin have potential to be the future universal memory technology, owing to zero leakage, high density, almost unlimited endurance and acceptable dynamic power consumption. In this article, we present device, circuit and architectural solutions to mitigate some of the challenges associated with spin-transfer-torque magnetic random access memories (STT-MRAMs),...
This paper proposes a functional safety methodology applied to fault tolerance in FPGA applications by evaluating a case study in digital signal processing (DSP) field. This study is based on the safety standard IEC 61508 that states a safe system must be capable of detecting faults and it should have a safety mode. So, functional evaluations of a configurable DSP module were needed to define this...
Data logging applications, such as those deployed in satellite launchers to acquire telemetry data, may require compression algorithms to cope with large amounts of data as well as limited storage and communication capabilities. When commercial-off-the-shelf hardware components are used to implement such applications, radiation-induced soft errors may occur, especially during the last stages of the...
In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. This work presents a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional implementation steps during logic synthesis...
Fault injection experiments are a powerful aid to identify and fix problems in the design of fault tolerance mechanisms, particularly when performed at early development phases. For this purpose, it is important not only to classify the faults, but also to understand the different faulty behaviors. When an embedded system is considered, a common approach for analyzing the faulty behavior is to exploit...
This paper presents a fault injection system for performing fault injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. The proposed system takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility...
The integration of a diagnostic software-based self-test and a software-based self-repair method into a single statically scheduled superscalar processor is presented. The self-test method is used as start-up test in-the-field in order to detect and localize permanent faults in the processor. The determined fault state is handed over to a software-based self-repair program. This program adapts the...
Reliability in advanced CMOS devices is a critical issue that can supersede the benefits of technology shrinking process. The Probabilistic Transfer Matrix (PTM) is the basis of more common reliability evaluation models. This work presents a probabilistic model for stuck-on faults in combinational logic gates, considering the individual fault probability of each logic function input vector. It shows...
The process of measuring the quality of a fault model is a key ingredient for implementing effective verification/testing phases based on fault injection. Most of the existing approaches for the qualification of a fault model base their evaluation on the comparison of the achieved fault coverage against other code coverage metrics, or against the fault coverage achieved by different fault models,...
Functional, at-speed test vectors play a critical role in targeting circuit defects not easily detected by traditional scan vectors. Fault simulating these vectors is generally computationally expensive since these tests are often applied at the system level without individual testing of modules within the hierarchy. As a result, fault grading techniques have become necessary to judge the quality...
Multicore architectures are very appealing as they offer the capability of integrating federated architectures, where multiple independent computing elements are devoted to specific tasks, into a single device, allowing significant mass and power savings. Often, the tasks in the federated architectures are responsible for mixed criticalities tasks, i.e. some of them are mission-/safety-critical real-time...
The main reason to invest in 3D circuits adoption is the possibility of decrease the wire length, replacing horizontal wires by shorter vertical through-silicon-vias (called of TSVs). As a consequence, a better performance is expected and other optimizations also can be obtained in comparison with planar technology. In relation to 3D circuits, the networks-on-chip (NoCs) receiving special attention...
Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one cannot rely on them alone. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify...
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