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A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog...
We compared the electrical characteristics, including mobility and on -state current , of -poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights . The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length decreases, for devices with tall fins becomes worse, probably due to a high parasitic...
Influence of NiSi S/D incorporation on parasitic resistance (Rpara) fluctuation of FinFETs was investigated in detail. While the NiSi S/D enhances the on current of the FinFET thanks to the Rpara reduction, it also causes additional Rpara fluctuation. Through analysis of correlation of Rpara with fin thickness and gate-to-NiSi offset fluctuation, it is revealed that NiSi/n+-Si contact resistance component...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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