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In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the...
Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the...
In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of MHz, and in several cases exceeding the GHz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international...
Electromagnetic interference (EMI) forecast is a critical issue in the modern electronic systems. The conventional method of EMI forecast includes the resonance frequency and S parameter of single board itself. However, it was not enough to estimate the worst peak frequency of EMI accurately, because on-chip capacitance affects greatly on the resonance frequency. Therefore, the EMI forecast is required...
Parasitic inductance that exists in a package induces SSN (Simultaneous Switching Noise) and timing jitter. These noises cause malfunction of LSI and systems. The goal of this paper is to clarify the influence of the effective inductance of the package including mutual inductance by changing the number of simultaneously switching buffers and alternating adjacent buffers in the reverse direction each...
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage (ABV) modulation and zero cross-regulation (CR) operation is proposed in this paper. To achieve the advanced power supply function in system-on-a-chip (SoC), the N-type low-dropout LDO regulator (N-LDR) is placed behind the SIDO converter to suppress voltage ripple and to eliminate the CR problem of SIDO converter...
Godson-2H is a complex SOC of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1GHz processor core and abundant high and low speed peripheral IO interfaces. Large scale and extremely strict low power requirements make great challenges in the chip design phase. To meet low power constraints in different application scenarios,...
On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed...
In this paper, we describe design and implementation of the Dependable Responsive Multithreaded Processor (D-RMTP) SoC (System-on-a-Chip) and SiP (System-in-a-Package). The D-RMTP SoC provides almost all functions required for the humanoid robots, including a real-time processing unit, a real-time inter-node communication link with error correction, and various I/O peripherals. The D-RMTP SoC is implemented...
Year by year the number of installed PV Hybrid systems for professional village power supply and industrial applications like telecommunication applications is increasing. In 2007 about 50 MWp PV power has been installed world-wide in such systems. PV hybrid systems are more and more an upcoming issue.
Adverse effects of unreliable on-chip power supply delivery are exacerbated due to the rapid shrinking of device dimensions and the ever increasing power consumptions in nanometre-scale integration. Power supply integrity becomes a critical concern. Particularly, on-chip communication networks, such as networks-on-chip (NoC), dictates power dissipations and overall system performance in multi-core...
A non-contact rapid charging inductive power supply (IPS) system has been developed and tested as a charger for electric-driven vehicles (EdV). By using this system, EdV charging can be carried out safely, easily, and in a short period. Optimizing the track and pick up design of the IPS based on finite-element electromagnetic field analyses achieved significant improvements in efficiency (92%), weight...
Mixed signal SOCs with integrated RF and power management modules have some distinct requirements associated with them. They are often used in portable and battery operated consumer applications, which are extremely cost and power sensitive. This translates into a few unique design and test constraints on the amount of DFT logic integrated, the permissible test time, and power-up of individual modules...
Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The...
High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The...
In this paper we propose a fine-grain Adaptive Voltage and Frequency Scaling (LAVFS) architecture to optimize energy efficiency in presence of in-die variability. For each System-on-Chip power domain, we use a Dynamic Voltage Scaling technique called ‘Vdd-Hopping’ as efficient as DC/DC power converters but much easier to integrate and control at fine-grain. Unlike previous AVS schemes, the supply...
The Multi-Domain-Test is the new test strategy to resolve problems and limitations of the Multi-Site-Test and the Concurrent-Test. By this novel test strategy, test time can be reduced down to 50% of the Single-Site-Test with almost the same amount of tester resources. Cost Of Test (COT) can be lower than the Multi-Site-Test that is well used at productions.
This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35 µm process and occupies an area of 2.5mm×2.5mm and an on-chip inductor occupies an area of 1.5mm×1.5mm. At 900MHz,...
This paper proposes a compact DC-DC buck converter with low output power and very low quiescent current dissipation for use in an ultra-capacitor based wireless sensor networks (WSNs) nodes. This converter is controlled by a self-oscillation topology in order to achieve less silicon area and lower quiescent dissipation than the conventional designs. The work is implemented in the standard 0.35um CMOS...
The wakeup sequence for power gating techniques has become an important issue as the rush current typically causes a high voltage drop. This paper proposes a new wakeup scheme utilizing an on-chip detector which continuously monitors the power supply noise in real time. Therefore, this scheme is able to dynamically throttle the wakeup sequence according to ambient voltage level. As a result, even...
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