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Due to outsourcing of IC fabrication, chip supply contamination is a clear and present danger, of which hardware Trojans (HTs) pose the greatest threat. This paper reviews the limitation of existing gate level characterization approaches to HT detection and presents a new detection method with a faster estimation of gate scaling factors by solving the normal equation of linear regression model. The...
Simple and accurate models for Gate leakage current (Ig) in nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are proposed in this paper. The accurate modeling for Oxide Electric field (Eox) and Oxide voltage (Vox) due to Short Channel Effect (SCE) between the gate and inverted channel is the key for higher accuracy. The Oxide Potential drop due to the charges image at the interface...
This work presents a re-investigation of the electrical characterisation of Gate Induced Drain Leakage (GIDL) [1][2]. The limits of the previously proposed extraction methods are underlined and a new approach is introduced. This new approach enables a better extraction of the GIDL parameters compared to the conventional methods, provided that a new step of electric field extraction is used. Finally,...
A simple analytic model for the progressive breakdown (BD) dynamics of ultrathin) gate oxides is presented. It is shown how the interplay between series and parallel resistances that represent the breakdown path and its surroundings leads to a sigmoidal I-t characteristic compatible with experimental data. The analysis is carried out using the Lyapunov exponent and the potential function associated...
An accurate method for extracting the depth and the energy level of an oxide trap from random telegraph noise (RTN) in the gate-induced drain leakage (GIDL) current of a metal-oxide-semiconductor field-effect transistor (MOSFET) is developed, which correctly accounts for variation in surface potential and Coulomb energy. The technique employs trap capture and emission times defined from the characteristics...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
I-V characteristic of the HfO2/SiO2 stack gate MIS capacitor is investigated. The gate leakage current in HfO2/SiO2 stack gate MIS capacitor decreases after constant voltage stress, which is caused by electron trapping. By analyzing the experiment and calculation results, the main transport mechanisms of the gate leakage current in HfO2/SiO2 stack gate is presented. The different transport mechanisms...
This paper introduces a new approach to pattern dependent static current estimation in logic blocks. A static current model is first developed at the transistor level and then extended to the logic gate level and logic block level. Using these static current models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which...
Runtime leakage control techniques, such as power gating (PG) and body biasing (BB), have been applied in a coarse-grained manner traditionally. In order to enable more aggressive leakage reduction, researchers are seeking ways to control leakage with finer granularity. Our research proposes two novel methods, namely circuit clustering for temporal and spatial idleness exploitation, to systematically...
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been proposed as a critical figure of merit of RTPG. Our research introduces the definition of average EBT in a run-time environment. We develop a method to estimate the average EBT for any given circuit block, considering the...
The paper describes NMOS and PMOS translinear cell which multiplies the current signals and which can be used for the current-mode signal processing. The translinear cell consists of NMOS or PMOS transistors that are treated in the sub-threshold conduction region. In this region the transistors exhibit an exponential dependency of the drain current versus the gate voltage and thus the translinear...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named dynamic standby mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially...
We present the analysis of direct tunneling (DT) gate leakage current in a 25 nm channel length n-channel metal oxide semiconductor field effect transistor MOSFET using an ensemble full band Monte Carlo (FBMC) simulation which incorporates quantum effects using Schrodinger solver. The DT current is simulated and compared with quantum drift diffusion (DD) results using DESSIS. The FBMC simulations...
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