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This paper focuses on the influence of annealing process on the properties and microstructural evolution of through-silicon-via electroplating copper. Particular attention is paid to the interposer-related through-silicon-via applications, which is fabricated by via-last process with the diameter of 20 microns and above. A interposer was designed and fabricated with its diameter of 100 microns and...
A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12...
In this article we present the conception, technological fabrication and electrical characterization of 3D hybrid pixel detector modules based on read out chips (ROCs) with through silicon vias (TSVs) which are flip chip bonded onto silicon photon sensors for X-ray detection. The TSVs in the ROCs enable a vertical routing of their peripheral IOs to the back side where they are spread to a land grind...
The increasing demand for lighter, thinner and flexible electronic devices are resulting in complexity in design. The 2D or planner devices miniaturization is reaching to its limit continuing its complexity in interconnect circuits causing limitation inefficient performance. To overcome the problem of complex interconnection and to introduce the more Compact device, the generation of 3D package rises...
Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through...
An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all...
In this paper we will discuss a method of fabricating a 0.8um and 1.2um diameter, 10um deep tungsten through-silicon-vias (TSV) from the backside of a 200mm silicon wafer at 4um and 2um pitches. These high-density tungsten TSVs connect to a thin copper backend, such as a metal 1 layer (M1) which can be as thin as 1000Å. We've applied this technology on a CMOS wafer from a high volume foundry and inserted...
Electronic power systems follow the general trend of miniaturization and functional density. 3D technologies provide an interesting response if adapted to power specifications. In the framework of the ENIAC JU funded project Enhanced Power Pilot Line (EPPL), a new type of device has been proposed consisting of an H bridge of power transistors and a Si interposer. This paper presents an H bridge of...
Open through silicon vias are direct vertical connections between different integration levels of a chip which provide higher performances per unit area in three-dimensional integrated circuits. The reliability of such structures in integrated circuits constitutes an important issue in microelectronics. This paper deals with electromigration reliability and lifetime evaluation of open copper through...
For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain...
An ultra-thinning down to 2.6-um using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness and Cu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-um within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-um while no degradation...
The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level "device" side copper wiring, with line space (L/S) of = 2.5 µm, built using...
Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After...
Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring...
With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a...
Cu pumping is a potential reliability issue for through silicon via (TSV) based 2.5D and 3D integration, due to the CTE mismatch between silicon and copper. In this paper, we report the reliability assessment of Cu pumping treated at different annealing conditions. Cu pumping is simulated by finite element method to compare the effect of the overburden layer. The pumping of TSVs having a diameter...
TSV(Through Silicon Via) is promising interconnection for the next generation smartphone, driving assistance and medical care system because of its ability of high speed image processing and low energy consumption. Conventional TSV electrodeposition requires several 10 minutes to hour because of applying small current of less than 10 mA/cm2. We are able to electrodeposit the 6 μm diameter and depth...
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