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This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation...
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
This paper presents the concepts of FPNA and FPNN, used for the approximation of artificial neural networks in FPGAs and discusses the usage of TMR technique in order to reach a fault tolerance. The diagrams of the FPGA implementation are presented. The results of experiments determining the FPGA resources utilization with different usage of the TMR technique are provided.
Due to the features of FPGA architectures such as high performance and reconfiguration at run time, they have become remarkable contenders for many mission critical applications, much beyond rapid prototyping only. As the feature size of the semiconductor technology shrinks, also FPGA-based systems using underlying nano-technologies suffer from age-induced parameter deterioration that may finally...
In FPGA applications in space, implementations are generally protected using radiation-error mitigation techniques such as triple modular redundancy. For high-performance systems, such fault tolerance techniques can prove problematic due to large power overhead. This paper presents a case study on the Digital Receiver System (DRS) in the Netherlands-China Low-frequency Explorer (NCLE), which is implemented...
Faults occurring in the safety-critical systems can lead to the failure of the whole system and cause high economical losses or endanger human health. As an example, space, aerospace or medical systems which are working in the environment with increased occurrence of faults can serve. Fault avoidance and fault tolerance are the main techniques, the goal of which is to avoid such situations. This paper...
As the security is becoming more and more important these days, we still should not forget about reliability. When designing a cryptographic device for some mission-critical or another reliability demanding system, we need to make the device not only attack-resistant, but also fault-tolerant. There are many common fault-tolerant digital design techniques, however, it is questionable, how these techniques...
Reassuring fault tolerance in computing systems that contain FPGA devices is the most important problem for mission critical space components. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper, we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded with on-demand three level...
Brushless DC motor is widely used in the space industry owing to its high performance, but the complex application environment brings a lot of damage factors to the motor. For example, the space radiation may damage the circuit device, and strong electromagnetic fields may interfere with motor operation. Therefore, the high reliability of the motor system becomes increasingly important. In order to...
In October 2015, Kaituo-1 double satellites were successfully launched in Taiyuan Satellite Launch Center. In November 2016, MCX satellite was successfully launched in Jiuquan Satellite Launch Center. All these satellites mentioned above were designed by Aerospace Dongfanghong Development Ltd, Shenzhen, and running stably on orbit. What's more, the low cost satellite platform which adopted the highly...
This paper deals with a review of research works which have been recently carried out on the topic of real-time fault diagnosis of electromechanical systems. The proposed approaches rely mainly on the implementation of fault diagnosis algorithms in digital signal processors and field programmable gate arrays as well as usage of real-time simulators applied formerly in the context of hardware-in-the-loop...
Reliability evaluation of Commercial off-the-shelf (COTS) processors against faults induced by radiation is a challenging problem. Some alternatives have been proposed to radiation test but they are very time consuming and lack of the observability needed. This work analyses the possibility to use an HDL model for estimating applications dependability on Texas Instruments MSP430 processor early in...
Field Programmable Gate Arrays (FPGA) are susceptible to soft errors due to the shrinkage of feature size and reduction in core voltage which reduces the critical charge required to change the state of a circuit element. To improve the reliability and availability of the FPGA based designs used in Nuclear Power Plants special care has to be taken against these emerging risks. In this paper, the effects...
Triple Modular Redundancy (TMR) is the most widely used technique to increase the reliability of SRAM-based FPGAs. In this paper, we investigate the application of TMR directly in C language-based algorithms to be synthesized using High Level Synthesis (HLS) to generate hardened Register Transfer Level (RTL) designs. We analyze four different TMR designs implemented into a 28 nm SRAM-based FPGA from...
ARM processors are leaders in embedded systems, delivering high-performance Computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. This paper proposes a lockstep approach to protect against soft errors the dual-core ARM Cortex-A9 processor, which is a hard-core processor embedded into Xilinx Zynq-7000 FPGA. The lockstep is...
It is proposed fault tolerant logic cell — LUT FPGA according to concept of the functionally complete tolerant element (FCT). The FCT element (logic element with the redundancy basis) retains functional completeness in case of faults. FCT element allows to perform FPGA self-repair after faults. It is established, that in a number of cases the quadrupling of the LUT's transistors has more advantages...
The susceptibility to Single Event Upset (SEU) is very high for Configuration memory of SRAM based Field Programmable Gate Arrays (FPGA) compared to other FPGA resources. The reduction in feature sizes and core voltages leads to a reduction in the critical charge required to change the state of a memory cell. The SEUs cause failures in the system functionality implemented in FPGA. Fault tolerant techniques...
FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods...
This paper presents an approach to fault-tolerant systems design and synthesis based on High-level Synthesis (HLS). A description and evaluation of the impacts of HLS optimization methods are shown as well. The higher reliability is achieved through modification of input description in the C++ programming language on which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs, which...
This paper presents concepts of FPNN which can be used for the implementation of artificial neural networks in FPGAs and introduces fault tolerant techniques applied on this concept that are developed by the authors.
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