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The trend of using heterogeneous computing and HW/SW-Codesign approaches allows increasing performance significantly while reducing power consumption. One of the main challenges when combining multiple processing devices is the communication, as an inefficient communication configu-ration can pose a bottleneck to the overall system performance. To address this problem, we present a methodology that...
The present paper describes the design strategies conceived to implement a module able to accomplish different tasks in the baseband environment of a synthetic aperture radar (SAR). This module, called the FGM (Formatting and Gyro stabilizing Module), is part of the QUASAR project for UAVs [1], currently being developed at INTA’s radar laboratory [2]. The main features of the FGM can be resumed as...
Platforms that are based on heterogeneous architectures require an intelligent resource manager. An intelligent resource manager should be able to accurately predict the future workload of the system at hand and take it into consideration. In this paper, we show that there exist patterns in the interarrival times of resource requests, and that these patterns can be used for modeling and prediction...
Automated driving systems have to operate at the highest level of robustness and safety. Thus, redundancy and diversity of the deployed systems are inevitable in order to guarantee the functionality in any possible scenario. Today, the most used sensor technologies for environment perception are color cameras, radar, light detection and ranging (LIDAR), and ultrasonic sensors. This work evaluates...
Dependability models are focused only on the basic stuck-at faults. In previous work a method has been shown on how to calculate dependability prediction using Markov chain models. This method has been described using the TMR architecture. In this paper a similar method for calculating the dependability parameter lambda (i.e., the failure rate of the system) is proposed. Focus is given on the dependability...
Over the last 30 years, a number of secure processor architectures have been proposed to protect software integrity and confidentiality during its distribution and execution. In such architectures, encryption (together with integrity checking) is used extensively, on any data leaving a defined secure boundary.In this paper, we show how encryption can be achieved at the instruction level using a stream...
Exploiting at best every bit of memory on chip is a must for finding the best trade-off between cost and performance when designing Many-Core MPSoCs. In this paper, we propose a new memory hierarchy organization that maximizes the usage of the available memory at each cache level while avoiding data redundancy. We also aim to reduce data access time by avoiding data migration. Our scheme is based...
Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores. Studies have shown that unutilized router buffers lead to significant network performance degradation. This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared...
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW...
The efficient protection of security critical devices against side-channel analysis attacks is a fundamental need in the age of Internet of Things and ubiquitous computing. In this work, we introduce a configurable hardware design of KECCAK (SHA-3) which can be tailored to fulfill the needs of a wide range of different applications. Our KECCAK design is therefore equipped with generic side-channel...
In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard .tcl interface...
Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100 Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources...
Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly...
The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture...
Reducing the inter-vehicle separation in a platoon results in the most benefits in terms of aerodynamic savings and vehicles throughput. However, this makes braking maneuvers dangerous and leads to long stopping distances, in particular, when considering heterogeneous vehicles with different braking capacities. Even though control theoretic approaches exist for the platoon cruise operation, the scenario...
Sophisticated embedded systems are increasingly used in defence, aerospace and avionic industries. They are responsible for control, collision avoidance, pilot assistance, target tracking, navigation and communications, amongst other functions. In this industrial field, High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons...
Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so...
Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
Power management becomes an integral part of hardware-systems design. In modern complex systems, the powermanagement design is not a simple task and it is quite difficult to evaluate whether the designed strategy is the best. In this paper, we propose a new method for overhead estimation of the required power-management unit, based on system-level abstract specification. It enables a designer to explore...
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