The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Most of the literature on image filtering using FPGAs focuses on the normal case when the window is completely within the image. The exception - when the window is partly off the edge of the image - is rarely considered. If not managed appropriately, handling these exceptions can take up more resources than the main operation. Efficient techniques are presented that manage the image borders by reusing...
In this paper, we propose an approach for detecting line segments in real-time by merging fixed-size short line segments. In many hardware systems, a Hough Transform has been used for detecting line segments. The Hough Transform is robust to noises, but it requires large memory space, and more space is required for images with higher resolution. Line detection is a primitive task which is frequently...
A multi-channel image superimposition system is designed in this paper. It can superimpose white-light image on infrared thermal image to generate mixture image. The system is realized on a FPGA chip and is mainly composed of multi-channel DMA controller and image superimposition module. Multi-channel DMA controller can realize data exchange between image superimpositon module and memory independent...
Impulse noise removal is a very important preprocessing operation in many computer vision applications. This paper presents a noise removal approach based on a simple conditional technique. As evaluations show, the presented technique performs significantly better than standard median filter and achieves superior image quality. Experimental FPGA implementation of the proposed technique for window...
The H.264/AVC standard achieves much higher coding efficiency than previous video coding standards. Unfortunately mis comes with a cost in considerably increased complexity at the encoder mainly due to motion estimation. Therefore, various fast algorithms have been proposed for reducing computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose...
In this paper we propose a hardware solution by the use of FPGA based circuit for real time face detection. We have built a sub-window architecture for the extraction of Haar-like features, which are the basic elements of weak classifiers according to AdaBoost learning algorithm. The main contribution is that the proposed architecture removes traditional frame buffer, and only reserve the line buffer...
Nowadays, embedded vision systems have to face new hard requirements involved by modern applications: real-time processing of high resolution images issued by multiple image sensors. Recently, a new adaptable ring-based interconnection network on chip has been proposed. Based on adaptive datapath, it allows handling of multiple parallel pixel streams. In this paper, we present a new hierarchical memory...
Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component...
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times...
In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity...
Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program...
In this paper a new FPGA design concept of a bilateral filter for image processing is presented. With the aid of this design the bilateral filter can be realized as a highly parallelized pipeline structure with very good utilization of dedicated resources. The innovation of the design concept lies in sorting the input data into groups in a manner that kernel based processing is possible. Another feature...
In this paper efficient hardware architecture for deblocking filter in H.264 is presented. A parallel filtering order is proposed without violating the standard, and the architecture is implemented in pipelined dataptah. With the parallel filtering order the vertical edges and horizontal edges can be processed simutaneously, and the filtering efficiency is improved. The memory is arranged and orgnized...
This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards - the sensor board, the USB board and the switch board - are used. As a verification method, 4-step verification strategy comprised...
Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection. However, its calculation cost is large because the feature vector for the CoHOG descriptor is very high-dimensional. In this paper, in order to achieve real-time detection on embedded systems, we propose a novel hardware architecture for the CoHOG feature extraction. Our architecture exploits...
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it...
Motion estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex...
This article presents a reconfigurable architecture to calculate a dense disparity map of two stereo images based on census transform. This architecture is simplified and efficient as a result of binary operations and integer arithmetic used by census transform. Our architecture was prototyped using GAUT which is a practical tool to develop high-level synthesis. We take advantage of GAUT rapid prototyping...
Field programmable gate arrays (FPGAs) are in use to build high performance image processing systems. This paper presents the design and implementation of such an open FPGA-based digital camera system for image capturing and real-time image processing. Images captured with a CMOS sensor are initially stored in the system's memory and then they are displayed on an LCD touch panel. The main goal of...
In this paper, an FPGA-based design and implementation of a high-performance video processing platform (VPP) is presented. A hardware/software codesign system is proposed on Xilinx Virtex II Pro FPGA to realize complex algorithms for real-time image and video processing. This paper presents the framework of the VPP, discusses the architectural building blocks and FPGA synthesis results. Each hardware...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.