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The following topics are dealt with: neurosynaptic integrated circuit; digital microfluidic biochips; supercomputer; flip-flops; ARM-FPGA; CPU; system-on-chips; vehicle intelligence; convolutional neural networks; silicon-on-insulator; STT-RAM; video signal processing; and CMOS integrated circuit.
With unique Flash*Freeze technology, the M1 IGLOO family of Actel FPGAs offers low power consumption, small footprint packages, reprogrammability and high capacity, and supports the 32-bit Cortex-M1 soft processor developed by ARM for implementation in FPGAs. Based on M1AGL600, a member of the M1 IGLOO family, a single-chip solution of embedded USB encryptor is proposed in this paper. Inside the M1AGL600,...
We propose a minimalistic processor architecture tailoring Wave Field Synthesis (WFS)-based audio applications to configurable hardware. Eleven high-level instructions provide the required flexibility for embedded WFS customization. We describe the implementation of the proposed instructions and apply them to a multi-core reconfigurable WFS architecture. Our approach combines software programming...
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
This paper describes a project undertaken to explore reconfigurable computing as a means to achieve high-throughput, low-power on-board computing for spacecraft. The solution consists of a reconfigurable data processor chip, a reconfigurable memory module, reconfigurable interconnect, and dynamic power management. The reconfigurable processor chip was fabricated in a 0.25 ?? bulk CMOS process using...
Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too much power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process. If we can implement the techniques for power reduction in front end process then we can easily design the low power...
Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider...
We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power...
This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction...
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using pseudo LRU (least recently used) algorithm...
Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, adapting a program designed to run on a sequential processor to be run instead on an FPGA can be time-consuming and difficult for anyone lacking significant experience in hardware design. In this paper we use a high-level...
Controllers implemented as finite-state machines (FSMs) occupy a major portion of FPGA designs. These FSMs can be implemented on synchronous embedded memory blocks (SEMBs) in current FPGAs. This approach, in addition to reducing considerable amount of power, also has several implementation benefits. In this research, we propose to further minimize the power consumed by the FSMs that are mapped to...
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific...
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