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This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor...
Integrated Modular Avionics (IMA) architecture provides means for integrating multiple safety-critical applications on a shared hardware in an airborne system. Error free data transfer between different modules of an IMA cabinet is an issue of critical importance. ARINC 659 has proven to be one of the most comprehensive standards for intra-cabinet data transfer within an IMA cabinet of commercial...
Although software engineers have high performance algorithms that could be implemented power-efficiently as embedded Systems on Chip (SoC) with modern FPGAs, there is still no easy path for them to a hardware realization, mainly due to the lack of appropriate design tools. We present an overview of a tool we have developed to boost the productivity of processor-centric SoC designs for FPGAs. Our tool...
This paper demonstrates the benefit of FPGAs for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems...
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
The system on a programmable chip (SoPC) based on FPGA has some special characteristics, such as flexibility, customization, programmable hardware and software. The design of user intellectual property (IP) core is an important task in the design of SoPC. This paper presents the design of image data compression IP core based on the standard of processor local bus (PLB). The IP core is based on CCSDS...
Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and creation of embedded multiprocessors architecture system focusing on its design area and performance. Embedded...
A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged...
Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation...
This article introduced the EDA technology development course, and has made certain description on its basic characteristic and the development process. Meanwhile this article has made the detailed introduction to the programmable logical component's present situation and the unique feature. It emphatically elaborated the present popular FPGA technology. This article aims at designing an independent...
Efficient design and implementation of an Fast Fourier Transform (FFT) processor is one of the most important problems for signal processing, signal transmission, networking and security (key enabling technologies supporting electrical and control engineering applications). The problems of design and implementation of complex numbers FFT processor based on the field programmable gate array (FPGA)...
Design and implementation of Fast Fourior Transform (FFT) processor is one of the most important problems for multimedia, communication, networking and security (key enabling technologies supporting E-Business and E-Government). The problems of design and implementation of complex numbers FFT processor based on field programmable gate array (FPGA) are studied for the application in the fields of multimedia,...
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance...
In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity...
In this paper, we describe the architecture of MipsCoreDuo, a microprocessor which is designed for LSI Design Contest in Okinawa 2009. MipsCoreDuo is a multifunction dual-core processor that has four attractive execution modes. It achieves high-parallel performance, high-sequential performance or high-dependability with single design. We implemented it in Verilog-HDL targeting an FPGA, and evaluated...
As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device. Most...
This paper presents a scheme of dual-port single memory controlling (DSMC) system based on switching, by which the dual-processor can access the shared single DDR SDRAM simultaneously and without collision. Therefore, the symmetric multi-processor (SMP) structure can utilize high-density, low-price DDR SDRAM as the shared memory to improve the system performance significantly. The DSMC system comprises...
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where...
This paper presents the implementation and delivery of a microprocessor based design laboratory, in an attempt to achieve tighter integration with theory and improve student's performance. The design process follows a hierarchical structure, requiring students to first build basic devices such as logic gates, multiplexers, one-bit memory cells etc. These basic devices are then used to build an ALU,...
Branch prediction is an important topic in modern computer architecture research. Predictors attempt to improve the performance of a processor with a reasonable hardware cost. In the last decade, many prediction schemes have been developed in order to achieve this objective, each of them with different cost/performance tradeoffs. Identifying the optimal predictor for a given architecture and set of...
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