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Energy minimization is of great importance in wireless sensor networks in extending the battery lifetime. One of the key activities of nodes in a WSN is communication and the routing of their data to a centralized base-station or sink. Routing using the shortest path to the sink is not the best solution since it will cause nodes along this path to fail prematurely. We propose a cross-layer energy...
Network routing is the mechanism chosen to send packets from any source to a destination in the network. The goal of any routing algorithm is to find an efficient path to send a packet to any destination taking into account all the obstacles that may be taking place in the network at any time. The focus of this paper is to provide an efficient solution to the routing problem by making use of reinforcement...
This paper presents an efficient algorithm to detect the global topological similarity between two circuits. By applying the proposed circuit similarity algorithm in an incremental design flow, IDUCS (incremental design using circuit similarity), the design and optimization effort in the previous design iterations is automatically captured and can be used to guide the next design iteration. IDUCS...
The resource locating efficiency is the core issue of P2P systems. The unstructured P2P systems adopt the flooding mechanism, which causes huge network burden. The Structured P2P systems, however, employs routing based on DHT, which results in an expensive topology maintenance. This paper will propose a semi-construct P2P model. Based on the research of the small world theory, this model combines...
In original Chord model,the semantic property of the content in the model is not taken into account. Besides,a node's logical ID is independent of its physical location,bringing tremendous delay to network routing.Aiming at the system instability of structured P2P model which is caused by the heterogeneity of nodes in model,this paper proposes a Structure P2P network based on the Chord (TI-CHORD)...
Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links...
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding,...
In multi-hop wireless networks, the way the network topology is defined has a strong impact on routing. This paper deals with topology control in cellular networks with relays. Several topology control algorithms taken from ad-hoc networks are adapted to cellular networks. Most of the algorithms considered here are based on proximity graphs. Performance analysis is carried out in a realistic scenario...
In this paper, we design a topology-agnostic adaptive routing algorithm for application-specific in routing table based NoC routers. The basic idea relies on using SCC(Strongly Connected Component) based methodology, which can be done in polynomial time, to guarantee deadlock free and using mean packets arrival rate on the paths to solve the problem of paths diversity. The efficiency of the proposed...
In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links,...
The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second-level mesh. Simulation results...
Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not...
Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy...
The safety vector [12] of a node in an n-cube, is a vector of n bits, each bit being a zero or 1. A value 1 in the kth bit of a node's safety vector guarantees a fault-free path to any node at Hamming distance k from it. In [13], it was shown that use of extended safety vector gives better performance at the cost of some extra computation. In this paper we have made a modification of the safety vector,...
This paper presents a router structure for Network-on-Chips called Quad Router which benefits from communication locality. The router can be shared among more than one Processing Element (PE), so the average hop count of a packet is decreased. This structure consists of eight input buffers and eight output ports by which two different topologies are introduced called Double-Link Mesh (DLM) and Crossbar...
Efficient on-chip communication is very important for exploiting enormous computing power available on a multi-core chip. Network on Chip (NoC) has emerged as a competitive candidate for implementing on-chip communication. Routing algorithms significantly affect the performance of a NoC. Most of the existing NoC architectural proposals advocate distributed routing algorithms for building NoC platforms...
Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to investigate new ideas or to customize the topology to application-specific needs. This paper analyzes existing mesh-type topologies and compares their characteristics in terms of communication and implementation costs. Furthermore,...
As technology advances, the number of cores in Chip Multi Processor systems (CMPs) and Multi Processor Systems-on-Chips (MPSoCs) keeps increasing. Current test chips and products reach tens of cores, and it is expected to reach hundreds of cores in the near future. Such complexity demands for an efficient network-on-chip (NoC). The common choice to build such networks is the 2D mesh topology (as it...
Fat-tree networks are the most popular topology among indirect networks in today's supercomputers. Current supercomputers are generally operated in a shared environment under the control of a job scheduler, executing many parallel applications simultaneously. The competition between these applications to use the same network resources causes a degradation in the applications' performance. The application...
Prior studies on packet-switching on-chip networks have primarily focused on the micro architecture of the router to reduce the communication latency. In this paper, we propose a novel interconnection topology for mesh-connected processor arrays. By sharing routers among PEs and PEs among routers, our network significantly reduces the average hop count for a packet, thereby reducing the network latency...
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