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Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to investigate new ideas or to customize the topology to application-specific needs. This paper analyzes existing mesh-type topologies and compares their characteristics in terms of communication and implementation costs. Furthermore,...
Current Network-on-Chip (NoC) architectures sometimes employ mesh or torus topology with the dimension-order routing. In this paper, we propose a deadlock-free routing algorithm, referred to as Balanced Dimension-Order Routing (BDOR), which provides the balanced minimal paths to each destination based on the simple routing regulations. Since the BDOR has the similar path regularity to that of the...
In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The automated generation of Network-on-Chip architectures covers beside the generation of the communication infrastructure, the automated integration of IP-components. The automated integration of IP-components is based on IP-XACT...
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as systems on a chip (SoC) and chip multiprocessor (CMP) designs, where even a single device failure can cause fatal system errors....
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast...
The fat-tree is one of the most widely-used topologies by interconnection network manufacturers. Recently, a deterministic routing algorithm that optimally balances the network traffic in fat--trees was proposed. It can not only achieve almost the same performance than adaptive routing, but also outperforms it for some traffic patterns. Nevertheless, fat-trees require a high number of switches with...
A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on...
The ubichip is a bio-inspired reconfigurable circuit developed in the framework of the European project Perplexus. The ubichip offers special reconfigurability capabilities, being the dynamic routing one of them. This paper describes how to exploit the dynamic routing capabilities of the ubichip in order to implement synaptogenetic neural networks. We present two techniques for dynamically generating...
The paper introduces a class of hierarchical interconnection networks, which is suitable for multicomputer systems. These networks, to which we give the name HFCube, employ the folded hypercube as a basic cluster, connect many such clusters using a complete graph, and maintain node connectivity to be the same for all nodes of the graph. We present all optimal routing algorithms for the HFCube. In...
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