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A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
This study presents a multi-touch sensing circuit for large-sized (more than 12 inches) capacitive touch panel. A new AC sensing technique is developed to enable the touch sensing in a large-sized capacitive touch panel. This novel designs of multi-touch sensing circuit lies in the operation principles through a 4X4 ITO film sensor array, a low-disturbance array circuit, a capacitance to voltage converter...
Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical...
We focus in this work on threshold logic gates (TLQ) implemented using double-gate (DG) MOSFETs. The proposed TLQ's can be programmed dynamically via secondary (back) gate using the same bias conditions as the primary (front) gate. Moreover, they can realize universal threshold logic functions, which comprise Boolean operations as a subset.
NATURE is a recently developed hybrid nano/CMOS reconfigurable architecture. It consists of complementary metal- oxide semiconductor (CMOS) reconfigurable logic and interconnect fabric, and carbon nanotube-based non-volatile on- chip configuration memory. Compared to existing CMOS- based field-programmable gate arrays (FPGAs), NATURE increases logic density by more than an order of magnitude and offers...
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